 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| this is information on a product in full production. march 2016 docid17478 rev 9 1/123 spc564bxx SPC56ECXX 32-bit mcu family built on the power architecture ? for automotive body electronics applications datasheet - production data features ? e200z4d, 32-bit power architecture ? ? up to 120 mhz and 200 mips operation ? e200z0h, 32-bit power architecture ? up to 80 mhz and 75 mips operation ? memory ? up to 3 mbyte on-chip flash with ecc ? up to 256 kbyte on-chip sram with ecc ? 64kbyte on-chip data flash with ecc ? 16-entry memory protection unit (mpu) ? user selectable memory bist ? interrupts ? 255 interrupt sources wi th 16 priority levels ? up to 54 ext. irq including 30 wake-up ? gpios: from 147 (lqfp176) to 199 (lbga256) ? system timer units ? 8-ch. 32-bit periodic interrupt timer (pit) ? 4-channel 32-bit system timer (stm) ? safety system watchdog timer (swt) ? real-time clock timer (rtc/api) ? emios, 16-bit counter timed i/o units ? up to 64 channels with pwm/mc/ic/oc ? two adc (10-bit and 12-bit) ? up to 62 channels extendable to 90 ch. ? multiple analog watchdog ? dedicated diagnostic features for lighting ? advanced shiffted pwm generation ? adc conversion synchronized on pwm ? communication interfaces ? up to 6 flexcan with 64 buffers each ? up to 10 linflex/uart channels ? up to 8 buffered dspi channels ?i 2 c interface ? one fleyray (dual-ch.) with 128 buffers ? fast ethernet controller ? cryptographic services engine (cse) ? aes-128 en/decryption, cmac auth. ? secured device boot mode ? 32-ch. edma with multiple request sources ? clock generation ? 4 to 40 mhz main oscillator ? 16 mhz internal rc oscillator ? software-controlled fmpll ? 128 khz internal rc oscillator ? 32 khz auxiliary oscillator ? clock monitoring unit (cmu) ? low power capabilities ? ultra low power standby ? can sampler to st ore can id in stby ? fast wake-up and exectute from ram ? exhaustive debugging capability ? nexus 3+ interface on lbga256 only ? nexus 1 on all devices ? voltage supply ? single 5 v or 3.3 v supply ? on-chip vreg with external ballast transitor ? operating temperature range -40 to 125 c lqfp176 (24 x 24 x 1.4 mm) lqfp208 (28 x 28 x 1.4 mm) lbga256 (17 x 17 x 1.7 mm) www.st.com
spc564bxx-SPC56ECXX 2/123 docid17478 rev 9 table 1. device summary package part number 1.5 mbyte 2 mbyte 3 mbyte lqfp176 spc564b64l7 spc56ec64l7 spc564b70l7 spc56ec70l7 spc564b74l7 spc56ec74l7 lqfp208 spc564b64l8 spc56ec64l8 spc564b70l8 spc56ec70l8 spc564b74l8 spc56ec74l8 lbga256 spc56ec64b3 spc56ec70b3 spc56ec74b3 docid17478 rev 9 3/123 spc564bxx-SPC56ECXX contents 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.1 nvusro [pad3v5v(0)] field description . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.2 nvusro [pad3v5v(1)] field description . . . . . . . . . . . . . . . . . . . . . . . 52 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.1 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.2 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6 i/o pad electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6.2 i/o input dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.6.3 i/o output dc characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6.4 output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6.5 i/o pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.7 reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.8 power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 67 3.8.1 voltage regulator electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . 67 3.8.2 vdd_bv options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.8.3 voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69 3.9 low voltage domain power consumption . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.10 flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72 contents spc564bxx-SPC56ECXX 4/123 docid17478 rev 9 3.10.1 program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.10.2 flash memory power supply dc characteristics . . . . . . . . . . . . . . . . . . 74 3.10.3 flash memory start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . 75 3.11 electromagnetic compatibility (emc) characteristics . . . . . . . . . . . . . . . . 75 3.11.1 designing hardened software to avoid noise problems . . . . . . . . . . . . . 75 3.11.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.11.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 76 3.12 fast external crystal oscillator (4?40 mhz) electrical characteristics . . . . 77 3.13 slow external crystal oscillator (32 khz) electrical characteristics . . . . . . 80 3.14 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.15 fast internal rc oscillator (16 mhz) elec trical characteristics . . . . . . . . . 83 3.16 slow internal rc oscillator (128 khz) el ectrical characteristics . . . . . . . . 85 3.17 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.18 fast ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.18.1 mii receive signal timing (rxd[3:0], rx_dv, rx_er, and rx_clk) . 96 3.18.2 mii transmit signal timing (txd[3:0 ], tx_en, tx_er, tx_clk) . . . . 97 3.18.3 mii async inputs signal timing (crs and col) . . . . . . . . . . . . . . . . . . 97 3.18.4 mii serial management channel timing (mdio and mdc) . . . . . . . . . . 98 3.19 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.19.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.19.2 dspi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.19.3 nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.19.4 jtag characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 4.2.1 lqfp176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.2 lqfp208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 112 4.2.3 lbga256 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 114 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 appendix a abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 docid17478 rev 9 5/123 spc564bxx-SPC56ECXX contents 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 list of tables spc564bxx-SPC56ECXX 6/123 docid17478 rev 9 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. spc564bxx and SPC56ECXX family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. spc564bxx and SPC56ECXX series block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. system pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 7. pad3v5v(0) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8. pad3v5v(1) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 10. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 11. recommended operating conditions (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 12. lqfp thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 13. lbga256 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 14. i/o input dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 15. i/o pull-up/pull-down dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 16. slow configuration output buffer electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . 60 table 17. medium configuration output buffer electrical ch aracteristics . . . . . . . . . . . . . . . . . . . . . . 61 table 18. fast configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 62 table 19. output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 20. i/o supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 21. i/o consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 22. reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 23. voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 24. low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 25. low voltage power domain electrical characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 26. code flash memory?program and erase specificatio ns . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 27. data flash memory?program and erase specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 28. flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 29. flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 30. flash memory power supply dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 31. start-up time/switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 32. emi radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 33. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 34. latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 35. crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 36. fast external crystal oscillator (4 to 40 mhz) electrical characteristics. . . . . . . . . . . . . . . . 79 table 37. crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 38. slow external crystal oscillato r (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . 82 table 39. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 40. fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 83 table 41. slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 85 table 42. adc input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 43. adc conversion characteristics (10-bit adc_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 44. conversion characteristics (12-bit adc_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 45. mii receive signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 46. mii transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 47. mii async inputs signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 48. mii serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 docid17478 rev 9 7/123 spc564bxx-SPC56ECXX list of tables 7 table 49. on-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 50. dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 51. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 52. jtag characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 53. lqfp176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 54. lqfp208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 55. lbga256 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 56. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 57. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 list of figures spc564bxx-SPC56ECXX 8/123 docid17478 rev 9 list of figures figure 1. spc564bxx and SPC56ECXX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. 176-pin lqfp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. 208-pin lqfp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. 256-pin bga configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. i/o input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 figure 6. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 7. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 8. voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 9. low voltage monitor vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 10. crystal oscillator and resonato r connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 11. fast external crystal oscillato r (4 to 40 mhz) electric al characteristics. . . . . . . . . . . . . . . . 79 figure 12. crystal oscillator and resonato r connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 13. equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 14. slow external crystal oscillato r (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . 82 figure 15. adc_0 characteristic and error de finitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 figure 16. input equivalent circuit (preci se channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 17. input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 18. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 19. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 20. adc_1 characteristic and error de finitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 figure 21. mii receive signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 22. mii transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 23. mii async inputs timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 24. mii serial management channel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 25. dspi classic spi timing?master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 26. dspi classic spi timing?master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 27. dspi classic spi timing?slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 28. dspi classic spi timing?slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 29. dspi modified transfer format timing?master, cp ha = 0. . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 30. dspi modified transfer format timing?master, cp ha = 1. . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 31. dspi modified transfer format timing?slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 32. dspi modified transfer format timing?slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 33. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 figure 34. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 35. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 36. timing diagram - jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 37. lqfp176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 38. lqfp208 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 39. lbga256 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 figure 40. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 docid17478 rev 9 9/123 spc564bxx-SPC56ECXX introduction 122 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the spc564bxx and SPC56ECXX device. to ensure a complete understanding of the device functionality, refer also to the spc564bxx and SPC56ECXX reference manual. 1.2 description the spc564bxx and SPC56ECXX is a new family of next generation microcontrollers built on the power architecture embedded category. th is document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. the spc564bxx and SPC56ECXX family expands the range of the spc560b microcontroller family. it provides the scalab ility needed to im plement platfo rm approaches and delivers the performance required by increa singly sophisticated software architectures. the advanced and cost-efficient host pr ocessor core of the spc564bxx and SPC56ECXX automotive controller family complies with the power ar chitecture embedded category, which is 100 percent user-mode compatible with the original power architecture user instruction set architecture (uisa). it operates at speeds of up to 120 mhz and offers high performance processing optimized for low powe r consumption. it also capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. introduction spc564bxx-SPC56ECXX 10/123 docid17478 rev 9 table 2. spc564bxx and SPC56ECXX family comparison (1) feature spc564b64 spc56ec64 spc564b70 spc56ec70 spc564b74 spc56ec74 package lqfp 176 lqfp 208 lqfp 176 lqfp 208 lbga 256 lqfp 176 lqfp 208 lqfp 176 lqfp 208 lbga 256 lqfp 176 lqfp 208 lqfp 176 lqfp 208 lbga 256 cpu e200z4d e200z4d + e200z0h e200z4d e200z 4d + e200z0h e200z4d e200z4d + e200z0h execution speed (2) up to 120 mhz (e200z4d) up to 120 mhz (e200z4d) up to 80 mhz (e200z0h) (3) up to 120 mhz (e200z4d) up to 120 mhz (e200z4d) up to 80 mhz (e200z0h) (3) up to 120 mhz (e200z4d) up to 120 mhz (e200z4d) up to 80 mhz (e200z0h) (3) code flash memory 1.5 mb 2 mb 3 mb data flash memory 4 x16 kb sram 128 kb 192 kb 160 kb 256 kb 192 kb 256 kb mpu 16-entry edma (4) 32 ch 10-bit adc 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch dedicated (5), (6) shared with 12-bit adc (7) 19 ch 12-bit adc 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch dedicated (8) shared with 10-bit adc (7) 19 ch ctu 64 ch total timer i/o (9) emios 64 ch, 16-bit sci (linflexd) 10 spi (dspi) 8 can (flexcan) (10) 6 spc564bxx-SPC56ECXX introduction docid17478 rev 9 11/123 flexray yes stcu (11) yes ethernet no yes no yes no yes i 2 c 1 32 khz oscillator (sxosc) yes gpio (12) 147 177 147 177 199 147 177 147 177 199 147 177 147 177 199 debug jtag nexus 3+ jtag nexus 3+ jtag nexus 3+ cryptographic services engine (cse) optional 1. feature set dependent on selected peripheral multiplexing; table shows example. 2. based on 125 ? c ambient operating temperature and subj ect to full device characterization. 3. the e200z0h can run at speeds up to 80 mhz. however, if syst em frequency is >80 mhz (e.g., e200z4d running at 120 mhz) the e2 00z0h needs to run at 1/2 system frequency. there is a configurable e200z0 system clock divider for this purpose. 4. dmamux also included that allows for softwa re selection of 32 out of a possible 57 sources. 5. not shared with 12-bit adc, but possibl y shared with other alternate functions. 6. there are 23 dedicated ans plus 4 dedicated anx channels on lq pf176. for higher pin count packages, there are 29 dedicated an s plus 4 dedicated anx channels. 7. 16x precision channels (a np) and 3x standard (ans). 8. not shared with 10-bit adc, but possibl y shared with other alternate functions. 9. as a minimum, all timer channels can function as pwm or input capture and output control. refer to the emios section of the d evice reference manual for information on the channel configuration and functions. 10. can sampler also included that allows id of can message to be captured when in low power mode. 11. stcu controls mbist activation and reporting. 12. estimated i/o count for proposed pack ages based on multiplexing with peripherals. table 2. spc564bxx and SPC56ECXX family comparison (1) (continued) feature spc564b64 spc56ec64 spc564b70 spc56ec70 spc564b74 spc56ec74 package lqfp 176 lqfp 208 lqfp 176 lqfp 208 lbga 256 lqfp 176 lqfp 208 lqfp 176 lqfp 208 lbga 256 lqfp 176 lqfp 208 lqfp 176 lqfp 208 lbga 256 introduction spc564bxx-SPC56ECXX 12/123 docid17478 rev 9 1.3 block diagram figure 1 shows the detailed block di agram of the spc564bxx and SPC56ECXX. figure 1. spc564bxx and SPC56ECXX block diagram 8 ? dspi fmpll nexus 3+ sram siul reset control 2 ? 128 kb external imux gpio & jtagc pad control jtag port nexus port e200z0h interrupt requests 64-bit 8 x 5 crossbar switch 6 ? flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi1 swt 8 ? 4 ? stm nmi1 intc i 2 c 10 ? linflexd 27 ch or 33 ch (2) mpu cmu 2 ? sram flash memory code flash 2 ? 1.5 mb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc/api sscm (master) (master) (slave) (slave) (slave) controller controller adc analog-to-digital converter bam boot assist module cse cryptographic services engine can controller area network (flexcan) cmu clock monitor unit ctu cross triggering unit dmamux dma channel multiplexer dspi deserial serial peripheral interface edma enhanced direct memory access flexcan controller area network controller modules fec fast ethernet controller emios enhanced modular input output system ecsm error correction status module fmpll frequency-modulated phase-locked loop flexray flexray communication controller i2c inter-integrated circuit bus imux internal multiplexer intc interrupt controller mpu ecsm from peripheral registers blocks emios e200z4d nexus 3+ nexus cse fec flexray wkp 16 x semaphores stcu nmi0 nmi0 instructions (master) data (master) adc 1 ? 10-bit can sampler adc 10 ch (1) 1 ? 12-bit pit rti 2 ? 32 ch dmamux (3) (3) notes: 1) 10 dedicated channels plus up to 19 shared channels . see the device-comparison table. 2) package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. see the device-comparison table. 3) (master) edma 16 x precision channels (anp) are mapped on input only i/o cells. jtagc jtag controller linflexd local interconnect network flexible with dma sup mc_me mode entry module mc_cgm clock generation module mc_pcu power control unit mc_rgm reset generation module mpu memory protection unit nexus nexus development interface nmi non-maskable interrupt pit_rti periodic interrupt timer with real-time interrupt rtc/api real-time clock/ autonomous periodic interrupt siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer stcu self test control unit wkpu wakeup unit legend: docid17478 rev 9 13/123 spc564bxx-SPC56ECXX introduction 122 table 3 summarizes the functions of the blocks present on the spc564bxx and SPC56ECXX. table 3. spc564bxx and SPC56ECXX series block summary block function analog-to-digital converter (adc) converts analog voltages to digital values boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock monitor unit (cmu) monitors clock so urce (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conver sions with a timer event from the emios or from the pit cryptographic security engine (cse) supports the encoding and decoding of any kind of data crossbar (xbar) switch supports simultaneous connections betwe en two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width dma channel multiplexer (dmamux) allows to route dma sources (called slots) to dma channels deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for ex iting sleep modes, and optional features such as information on memory erro rs reported by error-correcting codes enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ?n? programmable channels. enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol fmpll (frequency-modulated phase-locked loop) generates high-speed system clocks a nd supports programmable frequency modulation flexray (flexray communication controller) provides high-speed distributed contro l for advanced automotive applications fast ethernet controller (fec) ethernet media access controller (mac) designed to support both 10 and 100 mbps ethernet/i eee 802.3 networks internal multiple xer (imux) siul subblock allows flexible mapping of peripheral in terface on the different pins of the device inter-integrated circuit (i 2 c?) bus a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices interrupt controller (intc) provides priority-based preemptive sch eduling of interrupt requests for both e200z0h and e200z4d cores jtag controller provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode introduction spc564bxx-SPC56ECXX 14/123 docid17478 rev 9 linflexd (local interconnect network flexible with dma support) manages a high number of lin (loc al interconnect network protocol) messages efficiently with a minimum of cpu load memory protection unit (mpu) provides hardware access control for all memory references generated in a device clock generation module (mc_cgm) provides logic and control required fo r the generation of system and peripheral clocks power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power dom ains? which are controlled by the pcu reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional st ates; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications non-maskable interrupt (nmi) handles external events that must pr oduce an immediate response, such as power down detection nexus development interface (ndi) provides real-time development capabilities for e200z0h and e200z4d core processor periodic interrupt timer/ real time interrupt timer (pit_rti) produces periodic interrupts and triggers real-time counter (rtc/api) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-po wer mode). supports autonomous periodic interrupt (api) function to gener ate a periodic wakeup request to exit a low power mode or an interrupt request static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-pur pose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configuration and stat us data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar and operating system tasks semaphores provides the hardware support neede d in multi-core systems for sharing resources and provides a simple mechan ism to achieve lock/unlock operations via a single write access. wake unit (wkpu) supports external sources that can ge nerate interrupts or wakeup events, of which can cause non-maskable interrupt requests or wakeup events. table 3. spc564bxx and SPC56ECXX series block summary (continued) block function docid17478 rev 9 15/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 2 package pinouts and signal descriptions the available lqfp pinouts and the lbga ballmaps are provided in the following figures. for functional port pin description, see table 6 . figure 2. 176-pin lqfp configuration lqfp176 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pb[2] pc[8] pc[13] pc[12] pi[0] pi[1] pi[2] pi[3] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv_a vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] pi[4] pi[5] ph[12] ph[11] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa[4] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv_a pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pj[3] pj[2] pj[1] pj[0] pi[15] pi[14] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] vdd_hv_a vss_hv pd[8] pb[4] pa[11] pa[10] pa[9] pa[8] pa[7] pe[13] pf[14] pf[15] vdd_hv_b vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa[3] pi[13] pi[12] pi[11] vdd_lv vss_lv pi[8] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] vdd_hv_adc1 vss_hv_adc1 pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pb[3] pc[9] pc[14] pc[15] pj[4] vdd_hv_a vss_hv ph[15] ph[13] ph[14] pi[6] pi[7] pg[5] pg[4] pg[3] pg[2] pa[2] pe[0] pa[1] pe[1] pe[8] pe[9] pe[10] pa[0] pe[11] vss_hv vdd_hv_a vss_hv reset vss_lv vdd_lv vrc_ctrl pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] note 1) vdd_hv_b supplies the io voltage domain for the pins pe[12], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg[0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], and pa[3]. 2)availability of port pin alternate functions depends on product selection. package pinouts and signal descriptions spc564bxx-SPC56ECXX 16/123 docid17478 rev 9 figure 3. 208-pin lqfp configuration lqfp208 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 ? 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 pb[3] pc[9] pc[14] pc[15] pj[4] vdd_hv_a vss_hv ph[15] ph[13] ph[14] p[i6] p[i7] pg[5] pg[4] pg[3] pg[2] pa[2] pe[0] pa[1] pe[1] pe[8] pe[9] pe[10] pa[0] pe[11] vss_hv vdd_hv_a vss_hv reset vss_lv vdd_lv vrc_ctrl pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pk[1] pk[2] pk[3] pk[4] pk[5] pk[6] pk[7] pk[8] pf[9] pf[8] pf[12] pc[6] pa[11] pa[10] pa[9] pa[8] pa[7] pe[13] pf[14] pf[15] vdd_hv_b vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa[3] pi[13] pi[12] pi[11] pi[10] vdd_lv vss_lv pi[9] pi[8] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_a vss_hv pd[12] vdd_hv_adc1 vss_hv_adc1 pb[11] pd[11] pd[10] pd[9] pj[5] pj[6] pj[7] pj[8] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pj[12] pj[11] pa[4] pk[0] pj[15] pj[14] pj[13] pa[13] pj[10] pj[9] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv_a pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pj[3] pj[2] pj[1] pj[0] pi[15] pi[14] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] vdd_hv_a vss_hv pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pl[0] pk[15] pk[14] pk[13] pk[12] pk[11] pk[10] pk[9] pi[0] pi[1] pi[2] pi[3] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv_a vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] pi[4] pi[5] ph[12] ph[11] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] note 1) vdd_hv_b supplies the io voltage domain for the pins pe[12], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg[0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], and pa[3]. 2) availability of port pin alternate functions depends on product selection. docid17478 rev 9 17/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 figure 4. 256-pin bga configuration 12345678910111213141516 a pc[15] pb[2] pc[13] pi[1] pe[7] ph[8] pe[2] pe[4] pc[4] pe[3] ph[9] pi[4] ph[11] pe[14] pa[10] pg[11] a b ph[13] pc[14] pc[8] pc[12] pi[3] pe[6] ph[5] pe[5] pc[5] pc[0] pc[2] ph[12] pg[10] pa[11] pa[9] pa[8] b c ph[14] vdd_hv _a pc[9] pl[0] pi[0] ph[7] ph[6] vss_lv vdd_hv _a pa[5] pc[3] pe[15] pg[14] pe[12] pa[7] pe[13] c d pg[5] pi[6] pj[4] pb[3] pk[15] pi[2] ph[4] vdd_lv pc[1] ph[10] pa[6] pi[5] pg[15] pf[14] pf[15] ph[2] d e pg[3] pi[7] ph[15] pg[2] vdd_lv vss_lv pk[10] pk[9] pm[1] pm[0] pl[15] pl[14] pg[0] pg[1] ph[0] vdd_hv _a e f pa[2] pg[4] pa[1] pe[1] pl[2] pm[6] pl[1] pk[11] pm[5] pl[13] pl[12] pm[2] ph[1] ph[3] pg[12] pg[13] f g pe[8] pe[0] pe[10] pa[0] pl[3] vss_hv vss_hv vss_hv vss_hv vss_hv vss_hv pk[12] vdd_hv _b pi[13] pi[12] pa[3] g h pe[9] vdd_hv _a pe[11] pk[1] pl[4] vss_lv vss_lv vss_hv vss_hv vss_hv vss_hv pk[13] vdd_hv _a vdd_lv vss_lv pi[11] h j vss_hv vrc_ct rl vdd_lv pg[9] pl[5] vss_lv vss_lv vss_lv vss_hv vss_hv vss_hv pk[14] pd[15] pi[8] pi[9] pi[10] j k reset vss_lv pg[8] pc[11] pl[6] vss_lv vss_lv vss_lv vss_lv vdd_lv vdd_lv pm[3] pd[14] pd[13] pb[14] pb[15] k l pc[10] pg[7] pb[0] pk[2] pl[7] vss_lv vss_lv vss_lv vss_lv vdd_lv vdd_lv pm[4] pd[12] pb[12] pb[13] vdd_hv _adc1 l m pg[6] pb[1] pk[4] pf[9] pk[5] pk[6] pk[7] pk[8] pl[8] pl[9] pl[10] pl[11] pb[11] pd[10] pd[11] vss_hv _adc1 m n pk[3] pf[8] pc[6] pc[7] pj[13] vdd_hv _a pb[10] pf[6] vdd_hv _a pj[1] pd[2] pj[5] pb[5] pb[6] pj[6] pd[9] n p pf[12] pf[10] pf[13] pa[14] pj[9] pa[12] pf[0] pf[5 ] pf[7] pj[3] pi[15] pd[4] pd[7] pd[8] pj[8] pj[7] p r pf[11] pa[15] pj[11] pj[15] pa[13] pf[2] pf[3] pf [4] vdd_lv pj[2] pj[0] pd[0] pd[3] pd[6] vdd_hv _adc0 pb[7] r t pj[12] pa[4] pk[0] pj[14] pj[10] pf[1] xtal extal vss_lv pb[9] pb[8] pi[14] pd[1] pd[5] vss_hv _adc0 pb[4] t 12345678910111213141516 notes: 1) vdd_hv_b supplies the io voltage domain for the pins pe[12], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg [0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], pa[3], pm[3], and pm[4]. 2)availability of port pin alternate functions depends on product selection. package pinouts and signal descriptions spc564bxx-SPC56ECXX 18/123 docid17478 rev 9 2.1 pad types in the device the following types of pads are available for system pins and functional port pins: s = slow (a) m = medium (a),(b) f = fast (a),(b) i = input only with analog feature (a) a = analog 2.2 system pins the system pins are listed in table 4 . a. see the i/o pad electrical characteri stics in the device datasheet for details. b. all medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. for example, fast/medium pad will be medium by defaul t at reset. similarly, slow/medium pad will be slow by default. only exception is pc[1] which is in medium conf iguration by default (refer to pcr.src in the reference manual, pad configuration registers (pcr0?pcr198)). table 4. system pin descriptions port pin function i/o direction pad type reset config. pin number lqfp 176 lqfp 208 lbga 256 reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull-up only after phase2 29 29 k1 extal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. ia (1) ?5874t8 xtal analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. ? analog input for the clock generator when the oscillator is in bypass mode. i/o a (1) ?5672t7 1. for analog pads, it is not recommended to enable ibe if apc is enabled to avoid extra current in middle range voltage. docid17478 rev 9 19/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 2.3 functional ports the functional port pins are listed in table 5 . table 5. functional port pin descriptions port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 pa[0] pcr[0] af0 af1 af2 af3 ? ? gpio[0] e0uc[0] clkout e0uc[13] wkpu[19] can1rx siul emios_0 mc_cgm emios_0 wkpu flexcan_1 i/o i/o o i/o i i m/s tristate 24 24 g4 pa[1] pcr[1] af0 af1 af2 af3 ? ? ? gpio[1] e0uc[1] ? ? wkpu[2] can3rx nmi[0] (3) siul emios_0 ? ? wkpu flexcan_3 wkpu i/o i/o ? ? i i i s tristate 19 19 f3 pa[2] pcr[2] af0 af1 af2 af3 ? ? gpio[2] e0uc[2] ? ma[2] wkpu[3] nmi[1] (3) siul emios_0 ? adc_0 wkpu wkpu i/o i/o ? o i i s tristate 17 17 f1 pa[3] pcr[3] af0 af1 af2 af3 ? ? ? gpio[3] e0uc[3] lin5tx cs4_1 rx_er_clk eirq[0] adc1_s[0] siul emios_0 linflexd_5 dspi_1 fec siul adc_1 i/o i/o o o i i i m/s tristate 114 138 g16 pa[4] pcr[4] af0 af1 af2 af3 ? ? gpio[4] e0uc[4] ? cs0_1 lin5rx wkpu[9] siul emios_0 ? dspi_1 linflexd_5 wkpu i/o i/o ? i/o i i s tristate 51 61 t2 package pinouts and signal descriptions spc564bxx-SPC56ECXX 20/123 docid17478 rev 9 pa[5] pcr[5] af0 af1 af2 gpio[5] e0uc[5] lin4tx siul emios_0 linflexd_4 i/o i/o o m/s tristate 146 170 c10 pa[6] pcr[6] af0 af1 af2 af3 ? ? gpio[6] e0uc[6] ? cs1_1 lin4rx eirq[1] siul emios_0 ? dspi_1 linflexd_4 siul i/o i/o ? o i i s tristate 147 171 d11 pa[7] pcr[7] af0 af1 af2 af3 ? ? ? gpio[7] e0uc[7] lin3tx ? rxd[2] eirq[2] adc1_s[1] siul emios_0 linflexd_3 ? fec siul adc_1 i/o i/o o ? i i i m/s tristate 128 152 c15 pa[8] pcr[8] af0 af1 af2 af3 ? ? ? ? gpio[8] e0uc[8] e0uc[14] ? rxd[1] eirq[3] abs[0] lin3rx siul emios_0 emios_0 ? fec siul mc_rgm linflexd_3 i/o i/o i/o ? i i i i m/s input, weak pull-up 129 153 b16 pa[9] pcr[9] af0 af1 af2 af3 ? ? gpio[9] e0uc[9] ? cs2_1 rxd[0] fab siul emios_0 ? dspi1 fec mc_rgm i/o i/o ? o i i m/s pull- down 130 154 b15 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 21/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pa[10] pcr[10] af0 af1 af2 af3 ? ? ? gpio[10] e0uc[10] sda lin2tx col adc1_s[2] sin_1 siul emios_0 i 2 c linflexd_2 fec adc_1 dspi_1 i/o i/o i/o o i i i m/s tristate 131 155 a15 pa[11] pcr[11] af0 af1 af2 af3 ? ? ? ? gpio[11] e0uc[11] scl ? rx_er eirq[16] lin2rx adc1_s[3] siul emios_0 i 2 c ? fec siul linflexd_2 adc_1 i/o i/o i/o ? i i i i m/s tristate 132 156 b14 pa[12] pcr[12] af0 af1 af2 af3 ? ? gpio[12] ? e0uc[28] cs3_1 eirq[17] sin_0 siul ? emios_0 dspi1 siul dspi_0 i/o ? i/o o i i s tristate 53 69 p6 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 e0uc[29] ? siul dspi_0 emios_0 ? i/o o i/o ? m/s tristate 52 66 r5 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 e0uc[0] eirq[4] siul dspi_0 dspi_0 emios_0 siul i/o i/o i/o i/o i m/s tristate 50 58 p4 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 e0uc[1] wkpu[10] siul dspi_0 dspi_0 emios_0 wkpu i/o i/o i/o i/o i m/s tristate 48 56 r2 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 22/123 docid17478 rev 9 pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx e0uc[30] lin0tx siul flexcan_0 emios_0 linflexd_0 i/o o i/o i m/s tristate 39 39 l3 pb[1] pcr[17] af0 af1 af2 ? ? ? gpio[17] ? e0uc[31] lin0rx wkpu[4] can0rx siul ? emios_0 linflexd_0 wkpu flexcan_0 i/o ? i/o i i i s tristate 40 40 m2 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda e0uc[30] siul linflexd_0 i 2 c emios_0 i/o o i/o i/o m/s tristate 176 208 a2 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] e0uc[31] scl ? wkpu[11] lin0rx siul emios_0 i 2 c ? wkpu linflexd_0 i/o i/o i/o ? i i s tristate 1 1 d4 pb[4] pcr[20] af0 af1 af2 af3 ? ? gpi[20] ? ? ? adc0_p[0] adc1_p[0] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 88 104 t16 pb[5] pcr[21] af0 af1 af2 af3 ? ? gpi[21] ? ? ? adc0_p[1] adc1_p[1] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 91 107 n13 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 23/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pb[6] pcr[22] af0 af1 af2 af3 ? ? gpi[22] ? ? ? adc0_p[2] adc1_p[2] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 92 108 n14 pb[7] pcr[23] af0 af1 af2 af3 ? ? gpi[23] ? ? ? adc0_p[3] adc1_p[3] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 93 109 r16 pb[8] pcr[24] af0 af1 af2 af3 ? ? ? ? gpi[24] ? ? ? adc0_s[0] adc1_s[4] wkpu[25] osc32k_xtal (4) siul ? ? ? adc_0 adc_1 wkpu sxosc i ? ? ? i i i i i? 6177t11 pb[9] (5) pcr[25] af0 af1 af2 af3 ? ? ? ? gpi[25] ? ? ? adc0_s[1] adc1_s[5] wkpu[26] osc32k_extal ( 4) siul ? ? ? adc_0 adc_1 wkpu sxosc i ? ? ? i i i i i? 6076t10 pb[10] pcr[26] af0 af1 af2 af3 ? ? ? gpio[26] sout_1 can3tx ? adc0_s[2] adc1_s[6] wkpu[8] siul dspi_1 flexcan_3 ? adc_0 adc_1 wkpu i/o o ? ? i i i s tristate 62 78 n7 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 24/123 docid17478 rev 9 pb[11] pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 adc0_s[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? i/o i s tristate 97 117 m13 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 adc0_x[0] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 101 123 l14 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 adc0_x[1] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 103 125 l15 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 adc0_x[2] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 105 127 k15 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 adc0_x[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 107 129 k16 pc[0] (6) pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m/s input, weak pull-up 154 178 b10 pc[1] (6) pcr[33] af0 af1 af2 af3 gpio[33] ? tdo ? siul ? jtagc ? i/o ? o ? f/m tristate 149 173 d9 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 25/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx ? eirq[5] siul dspi_1 flexcan_4 ? siul i/o i/o o ? i m/s tristate 145 169 b11 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] ? can1rx can4rx eirq[6] siul dspi_1 adc_0 ? flexcan_1 flexcan_4 siul i/o i/o o i i i s tristate 144 168 c11 pc[4] pcr[36] af0 af1 af2 af3 alt4 ? ? ? gpio[36] e1uc[31] ? fr_b_tx_en sin_1 can3rx eirq[18] siul emios_1 ? flexray dspi_1 flexcan_3 siul i/o i/o ? o i i i m/s tristate 159 183 a9 pc[5] pcr[37] af0 af1 af2 af3 alt4 ? gpio[37] sout_1 can3tx ? fr_a_tx eirq[7] siul dspi_1 flexcan_3 ? flexray siul i/o o o ? o i m/s tristate 158 182 b9 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx e1uc[28] ? siul linflexd_1 emios_1 ? i/o o i/o ? s tristate 44 52 n3 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? e1uc[29] ? lin1rx wkpu[12] siul ? emios_1 ? linflexd_1 wkpu i/o ? i/o ? i i s tristate 45 53 n4 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 26/123 docid17478 rev 9 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx e0uc[3] ? siul linflexd_2 emios_0 ? i/o o i/o ? s tristate 175 207 b3 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? e0uc[7] ? lin2rx wkpu[13] siul ? emios_0 ? linflexd_2 wkpu i/o ? i/o ? i i s tristate 2 2 c3 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx ma[1] siul flexcan_1 flexcan_4 adc_0 i/o o o o m/s tristate 36 36 l1 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ma[2] can1rx can4rx wkpu[5] siul ? ? adc_0 flexcan_1 flexcan_4 wkpu i/o ? ? o i i i s tristate 35 35 k4 pc[12] pcr[44] af0 af1 af2 af3 alt4 ? ? gpio[44] e0uc[12] ? ? fr_dbg[0] sin_2 eirq[19] siul emios_0 ? ? flexray dspi_2 siul i/o i/o ? ? o i i m/s tristate 173 205 b4 pc[13] pcr[45] af0 af1 af2 af3 alt4 gpio[45] e0uc[13] sout_2 ? fr_dbg[1] siul emios_0 dspi_2 ? flexray i/o i/o o ? o m/s tristate 174 206 a3 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 27/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pc[14] pcr[46] af0 af1 af2 af3 alt4 ? gpio[46] e0uc[14] sck_2 ? fr_dbg[2] eirq[8] siul emios_0 dspi_2 ? flexray siul i/o i/o i/o ? o i m/s tristate 3 3 b2 pc[15] pcr[47] af0 af1 af2 af3 alt4 gpio[47] e0uc[15] cs0_2 ? fr_dbg[3] eirq[20] siul emios_0 dspi_2 ? flexray siul i/o i/o i/o ? o i m/s tristate 4 4 a1 pd[0] pcr[48] af0 af1 af2 af3 ? ? ? gpi[48] ? ? ? adc0_p[4] adc1_p[4] wkpu[27] siul ? ? ? adc_0 adc_1 wkpu i ? ? ? i i i i tristate 77 93 r12 pd[1] pcr[49] af0 af1 af2 af3 ? ? ? gpi[49] ? ? ? adc0_p[5] adc1_p[5] wkpu[28] siul ? ? ? adc_0 adc_1 wkpu i ? ? ? i i i itristate 78 94 t13 pd[2] pcr[50] af0 af1 af2 af3 ? ? gpi[50] ? ? ? adc0_p[6] adc1_p[6] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 79 95 n11 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 28/123 docid17478 rev 9 pd[3] pcr[51] af0 af1 af2 af3 ? ? gpi[51] ? ? ? adc0_p[7] adc1_p[7] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 80 96 r13 pd[4] pcr[52] af0 af1 af2 af3 ? ? gpi[52] ? ? ? adc0_p[8] adc1_p[8] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 81 97 p12 pd[5] pcr[53] af0 af1 af2 af3 ? ? gpi[53] ? ? ? adc0_p[9] adc1_p[9] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 82 98 t14 pd[6] pcr[54] af0 af1 af2 af3 ? ? gpi[54] ? ? ? adc0_p[10] adc1_p[10] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 83 99 r14 pd[7] pcr[55] af0 af1 af2 af3 ? ? gpi[55] ? ? ? adc0_p[11] adc1_p[11] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 84 100 p13 pd[8] pcr[56] af0 af1 af2 af3 ? ? gpi[56] ? ? ? adc0_p[12] adc1_p[12] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 87 103 p14 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 29/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pd[9] pcr[57] af0 af1 af2 af3 ? ? gpi[57] ? ? ? adc0_p[13] adc1_p[13] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 94 114 n16 pd[10] pcr[58] af0 af1 af2 af3 ? ? gpi[58] ? ? ? adc0_p[14] adc1_p[14] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 95 115 m14 pd[11] pcr[59] af0 af1 af2 af3 ? ? gpi[59] ? ? ? adc0_p[15] adc1_p[15] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 96 116 m15 pd[12] pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? adc0_s[4] siul dspi_0 emios_0 ? adc_0 i/o o i/o ? i s tristate 100 120 l13 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? adc0_s[5] siul dspi_1 emios_0 ? adc_0 i/o i/o i/o ? i s tristate 102 124 k14 pd[14] pcr[62] af0 af1 af2 af3 alt4 ? gpio[62] cs1_1 e0uc[26] ? fr_dbg[0] adc0_s[6] siul dspi_1 emios_0 ? flexray adc_0 i/o o i/o ? o i s tristate 104 126 k13 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 30/123 docid17478 rev 9 pd[15] pcr[63] af0 af1 af2 af3 alt4 ? gpio[63] cs2_1 e0uc[27] ? fr_dbg[1] adc0_s[7] siul dspi_1 emios_0 ? flexray adc_0 i/o o i/o ? o i s tristate 106 128 j13 pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? can5rx wkpu[6] siul emios_0 ? ? flexcan_5 wkpu i/o i/o ? ? i i s tristate 18 18 g2 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx ? siul emios_0 flexcan_5 ? i/o i/o o ? m/s tristate 20 20 f4 pe[2] pcr[66] af0 af1 af2 af3 alt4 ? ? gpio[66] e0uc[18] ? ? fr_a_tx_en sin_1 eirq[21] siul emios_0 ? ? flexray dspi_1 siul i/o i/o ? ? o i i m/s tristate 156 180 a7 pe[3] pcr[67] af0 af1 af2 af3 ? ? gpio[67] e0uc[19] sout_1 ? fr_a_rx wkpu[29] siul emios_0 dspi_1 ? flexray wkpu i/o i/o o ? i i m/s tristate 157 181 a10 pe[4] pcr[68] af0 af1 af2 af3 alt4 ? gpio[68] e0uc[20] sck_1 ? fr_b_tx eirq[9] siul emios_0 dspi_1 ? flexray siul i/o i/o i/o ? o i m/s tristate 160 184 a8 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 31/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pe[5] pcr[69] af0 af1 af2 af3 ? ? gpio[69] e0uc[21] cs0_1 ma[2] fr_b_rx wkpu[30] siul emios_0 dspi_1 adc_0 flexray wkpu i/o i/o i/o o i i m/s tristate 161 185 b8 pe[6] pcr[70] af0 af1 af2 af3 ? gpio[70] e0uc[22] cs3_0 ma[1] eirq[22] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m/s tristate 167 191 b6 pe[7] pcr[71] af0 af1 af2 af3 ? gpio[71] e0uc[23] cs2_0 ma[0] eirq[23] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m/s tristate 168 192 a5 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx e0uc[22] can3tx siul flexcan_2 emios_0 flexcan_3 i/o o i/o o m/s tristate 21 21 g1 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkpu[7] can2rx can3rx siul ? emios_0 ? wkpu flexcan_2 flexcan_3 i/o ? i/o ? i i i s tristate 22 22 h1 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 e1uc[30] eirq[10] siul linflexd_3 dspi_1 emios_1 siul i/o o o i/o i s tristate 23 23 g3 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 32/123 docid17478 rev 9 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] e0uc[24] cs4_1 ? lin3rx wkpu[14] siul emios_0 dspi_1 ? linflexd_3 wkpu i/o i/o o ? i i s tristate 25 25 h3 pe[12] pcr[76] af0 af1 af2 af3 ? ? ? ? gpio[76] ? e1uc[19] ? crs sin_2 eirq[11] adc1_s[7] siul ? emios_1 ? fec dspi_2 siul adc_1 i/o ? i/o ? i i i i m/s tristate 133 157 c14 pe[13] pcr[77] af0 af1 af2 af3 ? gpio[77] sout_2 e1uc[20] ? rxd[3] siul dspi_2 emios_1 ? fec i/o o i/o ? i m/s tristate 127 151 c16 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i m/s tristate 136 160 a14 pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] sck_6 siul dspi_2 emios_1 dspi_6 i/o i/o i/o i/o m/s tristate 137 161 c12 pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? adc0_s[8] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i s tristate 63 79 p7 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 33/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? adc0_s[9] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i s tristate 64 80 t6 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? adc0_s[10] siul emios_0 dspi_2 ? adc_0 i/o i/o i/o ? i s tristate 65 81 r6 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? adc0_s[11] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i s tristate 66 82 r7 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0uc[14] cs2_2 ? adc0_s[12] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i s tristate 67 83 r8 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? adc0_s[13] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i s tristate 68 84 p8 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] cs1_1 ? adc0_s[14] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i s tristate 69 85 n8 pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? cs2_1 ? adc0_s[15] siul ? dspi_1 ? adc_0 i/o ? o ? i s tristate 70 86 p9 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 34/123 docid17478 rev 9 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx cs4_0 can2tx siul flexcan_3 dspi_0 flexcan_2 i/o o o o m/s tristate 42 50 n2 pf[9] pcr[89] af0 af1 af2 af3 ? ? ? gpio[89] e1uc[1] cs5_0 ? can2rx can3rx wkpu[22] siul emios_1 dspi_0 ? flexcan_2 flexcan_3 wkpu i/o i/o o ? i i i s tristate 41 49 m4 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] cs1_0 lin4tx e1uc[2] siul dspi_0 linflexd_4 emios_1 i/o o o i/o m/s tristate 46 54 p2 pf[11] pcr[91] af0 af1 af2 af3 ? ? gpio[91] cs2_0 e1uc[3] ? lin4rx wkpu[15] siul dspi_0 emios_1 ? linflexd_4 wkpu i/o o i/o ? i i s tristate 47 55 r1 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] lin5tx ? siul emios_1 linflexd_5 ? i/o i/o o ? m/s tristate 43 51 p1 pf[13] pcr[93] af0 af1 af2 af3 ? ? gpio[93] e1uc[26] ? ? lin5rx wkpu[16] siul emios_1 ? ? linflexd_5 wkpu i/o i/o ? ? i i s tristate 49 57 p3 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 35/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pf[14] pcr[94] af0 af1 af2 af3 alt4 gpio[94] can4tx e1uc[27] can1tx mdio siul flexcan_4 emios_1 flexcan_1 fec i/o o i/o o i/o m/s tristate 126 150 d14 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? ? gpio[95] e1uc[4] ? ? rx_dv can1rx can4rx eirq[13] siul emios_1 ? ? fec flexcan_1 flexcan_4 siul i/o i/o ? ? i i i i m/s tristate 125 149 d15 pg[0] pcr[96] af0 af1 af2 af3 alt4 gpio[96] can5tx e1uc[23] ? mdc siul flexcan_5 emios_1 ? fec i/o o i/o ? o f tristate 122 146 e13 pg[1] pcr[97] af0 af1 af2 af3 ? ? ? gpio[97] ? e1uc[24] ? tx_clk can5rx eirq[14] siul ? emios_1 ? fec flexcan_5 siul i/o ? i/o ? i i i m tristate 121 145 e14 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] sout_3 ? siul emios_1 dspi_3 ? i/o i/o o ? m/s tristate 16 16 e4 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] cs0_3 ? wkpu[17] siul emios_1 dspi_3 ? wkpu i/o i/o i/o ? i s tristate 15 15 e1 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 36/123 docid17478 rev 9 pg[4] pcr[100] af0 af1 af2 af3 gpio[100] e1uc[13] sck_3 ? siul emios_1 dspi_3 ? i/o i/o i/o ? m/s tristate 14 14 f2 pg[5] pcr[101] af0 af1 af2 af3 ? ? gpio[101] e1uc[14] ? ? wkpu[18] sin_3 siul emios_1 ? ? wkpu dspi_3 i/o i/o ? ? i i s tristate 13 13 d1 pg[6] pcr[102] af0 af1 af2 af3 gpio[102] e1uc[15] lin6tx ? siul emios_1 linflexd_6 ? i/o i/o o ? m/s tristate 38 38 m1 pg[7] pcr[103] af0 af1 af2 af3 ? ? gpio[103] e1uc[16] e1uc[30] ? lin6rx wkpu[20] siul emios_1 emios_1 ? linflexd_6 wkpu i/o i/o i/o ? i i s tristate 37 37 l2 pg[8] pcr[104] af0 af1 af2 af3 ? gpio[104] e1uc[17] lin7tx cs0_2 eirq[15] siul emios_1 linflexd_7 dspi_2 siul i/o i/o o i/o i s tristate 34 34 k3 pg[9] pcr[105] af0 af1 af2 af3 ? ? gpio[105] e1uc[18] ? sck_2 lin7rx wkpu[21] siul emios_1 ? dspi_2 linflexd_7 wkpu i/o i/o ? i/o i i s tristate 33 33 j4 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 37/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pg[10] pcr[106] af0 af1 af2 af3 ? gpio[106] e0uc[24] e1uc[31] ? sin_4 siul emios_0 emios_1 ? dspi_4 i/o i/o i/o ? i s tristate 138 162 b13 pg[11] pcr[107] af0 af1 af2 af3 gpio[107] e0uc[25] cs0_4 cs0_6 siul emios_0 dspi_4 dspi_6 i/o i/o i/o i/o m/s tristate 139 163 a16 pg[12] pcr[108] af0 af1 af2 af3 alt4 gpio[108] e0uc[26] sout_4 ? txd[2] siul emios_0 dspi_4 ? fec i/o i/o o ? o m/s tristate 116 140 f15 pg[13] pcr[109] af0 af1 af2 af3 alt4 gpio[109] e0uc[27] sck_4 ? txd[3] siul emios_0 dspi_4 ? fec i/o i/o i/o ? o m/s tristate 115 139 f16 pg[14] pcr[110] af0 af1 af2 af3 ? gpio[110] e1uc[0] lin8tx ? sin_6 siul emios_1 linflexd_8 ? dspi_6 i/o i/o o ? i s tristate 134 158 c13 pg[15] pcr[111] af0 af1 af2 af3 ? gpio[111] e1uc[1] sout_6 ? lin8rx siul emios_1 dspi_6 ? linflexd_8 i/o i/o o ? i m/s tristate 135 159 d13 ph[0] pcr[112] af0 af1 af2 af3 alt4 ? gpio[112] e1uc[2] ? ? txd[1] sin_1 siul emios_1 ? ? fec dspi_1 i/o i/o ? ? o i m/s tristate 117 141 e15 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 38/123 docid17478 rev 9 ph[1] pcr[113] af0 af1 af2 af3 alt4 gpio[113] e1uc[3] sout_1 ? txd[0] siul emios_1 dspi_1 ? fec i/o i/o o ? o m/s tristate 118 142 f13 ph[2] pcr[114] af0 af1 af2 af3 alt4 gpio[114] e1uc[4] sck_1 ? tx_en siul emios_1 dspi_1 ? fec i/o i/o i/o ? o m/s tristate 119 143 d16 ph[3] pcr[115] af0 af1 af2 af3 alt4 gpio[115] e1uc[5] cs0_1 ? tx_er siul emios_1 dspi_1 ? fec i/o i/o i/o ? o m/s tristate 120 144 f14 ph[4] pcr[116] af0 af1 af2 af3 gpio[116] e1uc[6] sout_7 ? siul emios_1 dspi_7 ? i/o i/o o ? m/s tristate 162 186 d7 ph[5] pcr[117] af0 af1 af2 af3 ? gpio[117] e1uc[7] ? ? sin_7 siul emios_1 ? ? dspi_7 i/o i/o ? ? i s tristate 163 187 b7 ph[6] pcr[118] af0 af1 af2 af3 gpio[118] e1uc[8] sck_7 ma[2] siul emios_1 dspi_7 adc_0 i/o i/o i/o o m/s tristate 164 188 c7 ph[7] pcr[119] af0 af1 af2 af3 alt4 gpio[119] e1uc[9] cs3_2 ma[1] cs0_7 siul emios_1 dspi_2 adc_0 dspi_7 i/o i/o o o i/o m/s tristate 165 189 c6 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 39/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 ph[8] pcr[120] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc_0 i/o i/o o o m/s tristate 166 190 a6 ph[9] (6) pcr[121] af0 af1 af2 af3 ? gpio[121] ? ? ? tck siul ? ? ? jtagc i/o ? ? ? i s input, weak pull-up 155 179 a11 ph[10] (6) pcr[122] af0 af1 af2 af3 ? gpio[122] ? ? ? tms siul ? ? ? jtagc i/o ? ? ? i m/s input, weak pull-up 148 172 d10 ph[11] pcr[123] af0 af1 af2 af3 gpio[123] sout_3 cs0_4 e1uc[5] siul dspi_3 dspi_4 emios_1 i/o o i/o i/o m/s tristate 140 164 a13 ph[12] pcr[124] af0 af1 af2 af3 gpio[124] sck_3 cs1_4 e1uc[25] siul dspi_3 dspi_4 emios_1 i/o i/o o i/o m/s tristate 141 165 b12 ph[13] pcr[125] af0 af1 af2 af3 gpio[125] sout_4 cs0_3 e1uc[26] siul dspi_4 dspi_3 emios_1 i/o o i/o i/o m/s tristate 9 9 b1 ph[14] pcr[126] af0 af1 af2 af3 gpio[126] sck_4 cs1_3 e1uc[27] siul dspi_4 dspi_3 emios_1 i/o i/o o i/o m/s tristate 10 10 c1 ph[15] pcr[127] af0 af1 af2 af3 gpio[127] sout_5 ? e1uc[17] siul dspi_5 ? emios_1 i/o o ? i/o m/s tristate 8 8 e3 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 40/123 docid17478 rev 9 pi[0] pcr[128] af0 af1 af2 af3 gpio[128] e0uc[28] lin8tx ? siul emios_0 linflexd_8 ? i/o i/o o ? s tristate 172 196 c5 pi[1] pcr[129] af0 af1 af2 af3 ? ? gpio[129] e0uc[29] ? ? wkpu[24] lin8rx siul emios_0 ? ? wkpu linflexd_8 i/o i/o ? ? i i s tristate 171 195 a4 pi[2] pcr[130] af0 af1 af2 af3 gpio[130] e0uc[30] lin9tx ? siul emios_0 linflexd_9 ? i/o i/o o ? s tristate 170 194 d6 pi[3] pcr[131] af0 af1 af2 af3 ? ? gpio[131] e0uc[31] ? ? wkpu[23] lin9rx siul emios_0 ? ? wkpu linflexd_9 i/o i/o ? ? i i s tristate 169 193 b5 pi[4] pcr[132] af0 af1 af2 af3 gpio[132] e1uc[28] sout_4 ? siul emios_1 dspi_4 ? i/o i/o o ? m/s tristate 143 167 a12 pi[5] pcr[133] af0 af1 af2 af3 alt4 gpio[133] e1uc[29] sck_4 cs2_5 cs2_6 siul emios_1 dspi_4 dspi_5 dspi_6 i/o i/o i/o o o m/s tristate 142 166 d12 pi[6] pcr[134] af0 af1 af2 af3 alt4 gpio[134] e1uc[30] cs0_4 cs0_5 cs0_6 siul emios_1 dspi_4 dspi_5 dspi_6 i/o i/o i/o i/o i/o s tristate 11 11 d2 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 41/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pi[7] pcr[135] af0 af1 af2 af3 alt4 gpio[135] e1uc[31] cs1_4 cs1_5 cs1_6 siul emios_1 dspi_4 dspi_5 dspi_6 i/o i/o o o o s tristate 12 12 e2 pi[8] pcr[136] af0 af1 af2 af3 ? gpio[136] ? ? ? adc0_s[16] siul ? ? ? adc_0 i/o ? ? ? i s tristate 108 130 j14 pi[9] pcr[137] af0 af1 af2 af3 ? gpio[137] ? ? ? adc0_s[17] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 131 j15 pi[10] pcr[138] af0 af1 af2 af3 ? gpio[138] ? ? ? adc0_s[18] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 134 j16 pi[11] pcr[139] af0 af1 af2 af3 ? ? gpio[139] ? ? ? adc0_s[19] sin_3 siul ? ? ? adc_0 dspi_3 i/o ? ? ? i i s tristate 111 135 h16 pi[12] pcr[140] af0 af1 af2 af3 ? gpio[140] cs0_3 cs0_2 ? adc0_s[20] siul dspi_3 dspi_2 ? adc_0 i/o i/o i/o ? i s tristate 112 136 g15 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 42/123 docid17478 rev 9 pi[13] pcr[141] af0 af1 af2 af3 ? gpio[141] cs1_3 cs1_2 ? adc0_s[21] siul dspi_3 dspi_2 ? adc_0 i/o o o ? i s tristate 113 137 g14 pi[14] pcr[142] af0 af1 af2 af3 ? ? gpio[142] ? ? ? adc0_s[22] sin_4 siul ? ? ? adc_0 dspi_4 i/o ? ? ? i i stristate 76 92 t12 pi[15] pcr[143] af0 af1 af2 af3 ? gpio[143] cs0_4 cs2_2 ? adc0_s[23] siul dspi_4 dspi_2 ? adc_0 i/o i/o o ? i stristate 75 91 p11 pj[0] pcr[144] af0 af1 af2 af3 ? gpio[144] cs1_4 cs3_2 ? adc0_s[24] siul dspi_4 dspi_2 ? adc_0 i/o o o ? i stristate 74 90 r11 pj[1] pcr[145] af0 af1 af2 af3 ? ? gpio[145] ? ? ? adc0_s[25] sin_5 siul ? ? ?? adc_0 dspi_5 i/o ? ? ? i i s tristate 73 89 n10 pj[2] pcr[146] af0 af1 af2 af3 ? gpio[146] cs0_5 cs0_6 cs0_7 adc0_s[26] siul dspi_5 dspi_6 dspi_7 adc_0 i/o i/o i/o i/o i s tristate 72 88 r10 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 43/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pj[3] pcr[147] af0 af1 af2 af3 ? gpio[147] cs1_5 cs1_6 cs1_7 adc0_s[27] siul dspi_5 dspi_6 dspi_7 adc_0 i/o o o o i s tristate 71 87 p10 pj[4] pcr[148] af0 af1 af2 af3 gpio[148] sck_5 e1uc[18] ? siul dspi_5 emios_1 ? i/o i/o i/o ? m/s tristate 5 5 d3 pj[5] pcr[149] af0 af1 af2 af3 ? gpio[149] ? ? ? adc0_s[28] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 113 n12 pj[6] pcr[150] af0 af1 af2 af3 ? gpio[150] ? ? ? adc0_s[29] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 112 n15 pj[7] pcr[151] af0 af1 af2 af3 ? gpio[151] ? ? ? adc0_s[30] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 111 p16 pj[8] pcr[152] af0 af1 af2 af3 ? gpio[152] ? ? ? adc0_s[31] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 110 p15 pj[9] pcr[153] af0 af1 af2 af3 ? gpio[153] ? ? ? adc1_s[8] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 68 p5 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 44/123 docid17478 rev 9 pj[10] pcr[154] af0 af1 af2 af3 ? gpio[154] ? ? ? adc1_s[9] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 67 t5 pj[11] pcr[155] af0 af1 af2 af3 ? gpio[155] ? ? ? adc1_s[10] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 60 r3 pj[12] pcr[156] af0 af1 af2 af3 ? gpio[156] ? ? ? adc1_s[11] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 59 t1 pj[13] pcr[157] af0 af1 af2 af3 ? ? ? ? gpio[157] ? cs1_7 ? can4rx adc1_s[12] can1rx wkpu[31] siul ? dspi_7 ? flexcan_4 adc_1 flexcan_1 wkpu i/o ? o ? i i i i stristate ? 65 n5 pj[14] pcr[158] af0 af1 af2 af3 gpio[158] can1tx can4tx cs2_7 siul flexcan_1 flexcan_4 dspi_7 i/o o o o m/s tristate ? 64 t4 pj[15] pcr[159] af0 af1 af2 af3 ? gpio[159] ? cs1_6 ? can1rx siul ? dspi_6 ? flexcan_1 i/o ? o ? i m/s tristate ? 63 r4 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 45/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pk[0] pcr[160] af0 af1 af2 af3 gpio[160] can1tx cs2_6 ? siul flexcan_1 dspi_6 ? i/o o o ? m/s tristate ? 62 t3 pk[1] pcr[161] af0 af1 af2 af3 ? gpio[161] cs3_6 ? ? can4rx siul dspi_6 ? ? flexcan_4 i/o o ? ? i m/s tristate ? 41 h4 pk[2] pcr[162] af0 af1 af2 af3 gpio[162] can4tx ? ? siul flexcan_4 ? ? i/o o ? ? m/s tristate ? 42 l4 pk[3] pcr[163] af0 af1 af2 af3 ? ? gpio[163] e1uc[0] ? ? can5rx lin8rx siul emios_1 ? ? flexcan_5 linflexd_8 i/o i/o ? ? i i m/s tristate ? 43 n1 pk[4] pcr[164] af0 af1 af2 af3 gpio[164] lin8tx can5tx e1uc[1] siul linflexd_8 flexcan_5 emios_1 i/o o o i/o m/s tristate ? 44 m3 pk[5] pcr[165] af0 af1 af2 af3 ? ? gpio[165] ? ? ? can2rx lin2rx siul ? ? ? flexcan_2 linflexd_2 i/o ? ? ? i i m/s tristate ? 45 m5 pk[6] pcr[166] af0 af1 af2 af3 gpio[166] can2tx lin2tx ? siul flexcan_2 linflexd_2 ? i/o o o ? m/s tristate ? 46 m6 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 46/123 docid17478 rev 9 pk[7] pcr[167] af0 af1 af2 af3 ? ? gpio[167] ? ? ? can3rx lin3rx siul ? ? ? flexcan_3 linflexd_3 i/o ? ? ? i i m/s tristate ? 47 m7 pk[8] pcr[168] af0 af1 af2 af3 gpio[168] can3tx lin3tx ? siul flexcan_3 linflexd_3 ? i/o o o ? m/s tristate ? 48 m8 pk[9] pcr[169] af0 af1 af2 af3 ? gpio[169] ? ? ? sin_4 siul ? ? ? dspi_4 i/o ? ? ? i m/s tristate ? 197 e8 pk[10] pcr[170] af0 af1 af2 af3 gpio[170] sout_4 ? ? siul dspi_4 ? ? i/o o ? ? m/s tristate ? 198 e7 pk[11] pcr[171] af0 af1 af2 af3 gpio[171] sck_4 ? ? siul dspi_4 ? ? i/o i/o ? ? m/s tristate ? 199 f8 pk[12] pcr[172] af0 af1 af2 af3 gpio[172] cs0_4 ? ? siul dspi_4 ? ? i/o i/o ? ? m/s tristate ? 200 g12 pk[13] pcr[173] af0 af1 af2 af3 ? gpio[173] cs3_6 cs2_7 sck_1 can3rx siul dspi_6 dspi_7 dspi_1 flexcan_3 i/o o o i/o i m/s tristate ? 201 h12 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 47/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pk[14] pcr[174] af0 af1 af2 af3 gpio[174] can3tx cs3_7 cs0_1 siul flexcan_3 dspi_7 dspi_1 i/o o o i/o m/s tristate ? 202 j12 pk[15] pcr[175] af0 af1 af2 af3 ? ? gpio[175] ? ? ? sin_1 sin_7 siul ? ? ? dspi_1 dspi_7 i/o ? ? ? i i m/s tristate ? 203 d5 pl[0] pcr[176] af0 af1 af2 af3 gpio[176] sout_1 sout_7 ? siul dspi_1 dspi_7 ? i/o o o ? m/s tristate ? 204 c4 pl[1] pcr[177] af0 af1 af2 af3 gpio[177] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? f7 pl[2] pcr[178] (7) af0 af1 af2 af3 gpio[178] ? mdo0 (8) ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f5 pl[3] pcr[179] af0 af1 af2 af3 gpio[179] ? mdo1 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? g5 pl[4] pcr[180] af0 af1 af2 af3 gpio[180] ? mdo2 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? h5 pl[5] pcr[181] af0 af1 af2 af3 gpio[181] ? mdo3 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? j5 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 48/123 docid17478 rev 9 pl[6] pcr[182] af0 af1 af2 af3 gpio[182] ? mdo4 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? k5 pl[7] pcr[183] af0 af1 af2 af3 gpio[183] ? mdo5 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? l5 pl[8] pcr[184] af0 af1 af2 af3 ? gpio[184] ? ? ? evti siul ? ? ? nexus i/o ? ? ? i s pull-up ? ? m9 pl[9] pcr[185] af0 af1 af2 af3 gpio[185] ? mseo ? siul ? nexus ? i/o ? o ? m/s tristate ? ? m10 pl[10] pcr[186] af0 af1 af2 af3 gpio[186] ? mcko ? siul ? nexus ? i/o ? o ? f/s tristate ? ? m11 pl[11] pcr[187] af0 af1 af2 af3 gpio[187] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? m12 pl[12] pcr[188] af0 af1 af2 af3 gpio[188] ? evto ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f11 pl[13] pcr[189] af0 af1 af2 af3 gpio[189] ? mdo6 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f10 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 49/123 spc564bxx-SPC56ECXX package pino uts and signal descriptions 122 pl[14] pcr[190] af0 af1 af2 af3 gpio[190] ? mdo7 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e12 pl[15] pcr[191] af0 af1 af2 af3 gpio[191] ? mdo8 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e11 pm[0] pcr[192] af0 af1 af2 af3 gpio[192] ? mdo9 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e10 pm[1] pcr[193] af0 af1 af2 af3 gpio[193] ? mdo10 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e9 pm[2] pcr[194] af0 af1 af2 af3 gpio[194] ? mdo11 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f12 pm[3] pcr[195] af0 af1 af2 af3 gpio[195] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? k12 pm[4] pcr[196] af0 af1 af2 af3 gpio[196] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? l12 table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 package pinouts and signal descriptions spc564bxx-SPC56ECXX 50/123 docid17478 rev 9 pm[5] pcr[197] af0 af1 af2 af3 gpio[197] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? f9 pm[6] pcr[198] af0 af1 af2 af3 gpio[198] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? f6 1. alternate functions are chosen by setti ng the values of the pcr.pa bitfields inside the siul module. pcr.pa = 000 ? af0; pcr.pa = 001 ?? af1; pcr.pa = 010 ?? af2; pcr.pa = 011 ? af3; pcr.pa = 100 ? alt4. this is intended to select the output functions; to use one of the input functions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reas on, the value corresponding to an input only function is reported as ???. 2. multiple inputs are routed to all respective modules internal ly. the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 3. nmi[0] and nmi[1] have a higher priority than alternate functi ons. when nmi is selected, the pcr.pa field is ignored. 4. sxosc?s osc32k_xtal and osc32k_extal pins are shared wi th gpio functionality. when used as crystal pins, other functionality of the pin cannot be used a nd it should be ensured that application never programs obe and pue bit of the corresponding pcr to "1". 5. if you want to use osc32k functionality through pb[8] and pb[9], y ou must ensure that pb[10] is static in nature as pb[10] can induce coupling on pb[9] and disturb oscillator frequency. 6. out of reset all the functional pins except pc[0:1 ] and ph[9:10] are available to the user as gpio. ? pc[0:1] are available as jtag pi ns (tdi and tdo respectively). ? ph[9:10] are available as jtag pins (tck and tms respectively). ? it is up to the user to configure these pins as gpio when needed. 7. when mbist is enabled to run (stcu enable = 1), the application must not drive or tie pad[178) (mdo[0]) to 0 v before the device exits reset (external reset is removed) as the p ad is internally driven to 1 to indicate mbist operation. when mbist is not enabled (stcu enable = 0), there are no restri ction as the device does not internally drive the pad. 8. these pins can be configured as nexus pins during reset by the debugger writi ng to the nexus development interface "port control register" rather than the siul. specifically, the debugger can enable the mdo[7:0], mseo, and mcko ports by programming ndi (pcr[mcko_en] or pcr[pstat_en]). mdo[8:11] ports can be enabled by programming ndi ((pcr[mcko_en] and pcr[fpm]) or pcr[pstat_en]). table 5. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset config. pin number lqfp 176 lqfp 208 lbga256 docid17478 rev 9 51/123 spc564bxx-SPC56ECXX electrical characteristics 122 3 electrical characteristics this section contains electrical characterist ics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused i nputs can be driven to an appropriate logic voltage level (v dd or v ss_hv ). this could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables r epresent the characteristics of the device and its demands on the system. in the tables where the device logic prov ides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. 3.1 parameter classification the electrical parameters shown in this su pplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 6 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is s hown in the column labeled ?c? in the parameter tables where appropriate. 3.2 nvusro register portions of the device configuration, such as high voltage supply is controlled via bit values in the non-volatile user options register (nvusro). for a detailed description of the nvusro register, see spc564bxx and SPC56ECXX reference manual. table 6. paramete r classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size ac ross process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless othe rwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. electrical characteristics spc564bxx-SPC56ECXX 52/123 docid17478 rev 9 3.2.1 nvusro [pad3v5v(0)] field description table 7 shows how nvusro [pad3v5v(0)] cont rols the device configuration for v dd_hv_a domain. the dc electrical characteristics are dependent on the pad3v5v(0,1) bit value. 3.2.2 nvusro [pad3v5v(1)] field description table 8 shows how nvusro [pad3v5v(1)] controls the device configuration the device configuration for v dd_hv_b domain. the dc electrical characteristics are dependent on the pad3v5v(0,1) bit value. 3.3 absolute maximum ratings table 7. pad3v5v(0) field description value (1) description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v 1. '1' is delivery value. it is part of shadow flash memory, thus programmable by customer. table 8. pad3v5v(1) field description value (1) description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v 1. '1' is delivery value. it is part of shadow flash memory, thus programmable by customer. table 9. absolute maximum ratings symbol parameter conditions value unit min max v ss_hv s r digital ground on vss_hv pins ?00v v dd_hv_a s r voltage on vdd_hv_a pins with respect to ground (v ss_hv ) ??0.36.0v v dd_hv_b (1) s r voltage on vdd_hv_b pins with respect to common ground (v ss_hv ) ??0.36.0v v ss_lv s r voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss_hv ) ?v ss_hv ?? 0.1 v ss_hv ?? 0.1 v docid17478 rev 9 53/123 spc564bxx-SPC56ECXX electrical characteristics 122 note: stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly and functional operati on of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliabilit y. during overload conditions (v in > v dd_hv_a/hv_b or v in < v ss_hv ), the voltage on pins with respect to ground (v ss_hv ) must not exceed the recommended values. v rc_ctrl (2) base control voltage for external bcp68 npn device relative to v dd_lv 0v dd_lv + 1 v v ss_adc s r voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pin with respect to ground (v ss_hv ) ?v ss_hv ?? 0.1 v ss_hv + 0.1 v v dd_hv_adc0 s r voltage on vdd_hv_adc0 with respect to ground (v ss_hv ) ??0.36.0 v relative to v dd_hv_a (3) v dd_hv_a ?? 0.3 v dd_hv_a +0.3 v dd_hv_adc1 (4) s r voltage on vdd_hv_adc1 with respect to ground (v ss_hv ) ??0.36.0 v relative to v dd_hv_a 2 v dd_hv_a ? 0.3 v dd_hv_a +0.3 v in s r voltage on any gpio pin with respect to ground (v ss_hv ) relative to v dd_hv_a/hv_b v dd_hv_a/hv_b ? 0.3 v dd_hv_a/hv_b + 0.3 v i injpad s r injected input current on any pin during overload condition ??1010 ma i injsum s r absolute sum of all injected input currents during overload condition ??5050 i avgseg (5) s r sum of all the static i/o current within a supply segment (v dd_hv_a or v dd_hv_b ) v dd = 5.0 v 10%, pad3v5v = 0 70 ma v dd = 3.3 v 10%, pad3v5v = 1 64 t storage s r storage temperature ? ?55 (6) 150 c 1. v dd_hv_b can be independently controlled from v dd_hv_a . these can ramp up or ramp down in any order. design is robust against any supply order. 2. this voltage is internally generated by the dev ice and no external voltage should be supplied. 3. both the relative and the fixed condi tions must be met. for instance: if v dd_hv_a is 5.9 v, v dd_hv_adc0 maximum value is 6.0 v then, despite the relative condition, the max value is v dd_hv_a + 0.3 = 6.2 v. 4. pa3, pa7, pa10, pa11 and pe12 adc_1 channels are coming from v dd_hv_b domain hence v dd_hv_adc1 should be within 300 mv of v dd_hv_b when these channels are used for adc_1. 5. any temperature beyond 125 c should limit the current to 50 ma (max). 6. this is the storage temperature for the flash memory. table 9. absolute maximum ratings (continued) symbol parameter conditions value unit min max electrical characteristics spc564bxx-SPC56ECXX 54/123 docid17478 rev 9 3.4 recommended operating conditions table 10. recommended operating conditions (3.3 v) symbol parameter conditions value unit min max v ss_hv sr digital ground on vss_hv pins ?0 0v v dd_hv_a (1) sr voltage on v dd_hv_a pins with respect to ground (v ss_hv ) ?3.0 3.6v v dd_hv_b (1) sr voltage on v dd_hv_b pins with respect to ground (v ss_hv ) ?3.0 3.6v v ss_lv (2) sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss_hv ) ?v ss_hv ?? 0.1 v ss_hv + 0.1 v v rc_ctrl (3) base control voltage for external bcp68 npn device relative to v dd_lv 0v dd_lv + 1 v v ss_adc sr voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pin with respect to ground (v ss_hv ) ?v ss_hv ?? 0.1 v ss_hv + 0.1 v v dd_hv_adc0 (4) sr voltage on vdd_hv_adc0 with respect to ground (v ss_hv ) ?3.0 (5) 3.6 v relative to v dd_hv_a (6) v dd_hv_a ?? 0.1 v dd_hv_a + 0.1 v dd_hv_adc1 (7) sr voltage on vdd_hv_adc1 with respect to ground (v ss_hv ) ?3.0 3.6 v relative to v dd_hv_a (6) v dd_hv_a ?? 0.1 v dd_hv_a + 0.1 v in sr voltage on any gpio pin with respect to ground (v ss_hv ) ?v ss_hv ?? 0.1 ? v relative to v dd_hv_a/hv_b ?v dd_hv_a/hv_b + 0.1 i injpad sr injected input current on any pin during overload condition ? ? 55 ma i injsum sr absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd sr v dd_hv_a slope to ensure correct power up (8) ?? 0.5v/s ? 0.5 ? v/min docid17478 rev 9 55/123 spc564bxx-SPC56ECXX electrical characteristics 122 t a sr ambient temperature under bias f cpu up to 120 mhz ? 2% ?40 125 c t j sr junction temperature under bias ? ? 40 150 1. 100 nf emi capacitance need to be provided between each vdd/vss_hv pair. 2. 100 nf emi capacitance needs to be provided between each vdd_lv/vss_lv supply pair. 10 f bulk capacitance needs to be provided as creg on each vdd_lv pin. for detai ls refer to the power management chapter of the mpc5646c reference manual. 3. this voltage is internally generated by t he device and no external voltage should be supplied. 4. 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 5. full electrical specific ation cannot be guaranteed when voltage drops belo w 3.0 v. in particular, adc electrical characteristics and i/os dc electric al specification may not be guaranteed. when voltage drops below v lvdhvl , device is reset. 6. both the relative and the fixed conditions must be met. for instance: if v dd_hv_a is 5.9 v, v dd_hv_adc0 maximum value is 6.0 v then, despite the relative condition, the max value is v dd_hv_a + 0.3 = 6.2 v. 7. pa3, pa7, pa10, pa11 and pe12 adc_1 channels are coming from v dd_hv_b domain hence v dd_hv_adc1 should be within 100 mv of v dd_hv_b when these channels are used for adc_1. 8. guaranteed by the device validation. table 11. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max v ss_hv s r digital ground on vss_hv pins ? 0 0 v v dd_hv_a (1) s r voltage on vdd_hv_a pins with respect to ground (v ss_hv ) ?4.55.5 v voltage drop (2) 3.0 5.5 v dd_hv_b s r generic gpio functionality ? 3.0 5.5 v ethernet/3.3 v functionality (see the notes in all figures in section 2: package pinouts and signal descriptions for the list of channels operating in v dd_hv_b domain) ?3.03.6v v ss_lv (3) s r voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss_hv ) ?v ss_hv ? 0.1 v ss_hv + 0.1 v v rc_ctrl (4) base control voltage for external bcp68 npn device relative to v dd_lv 0v dd_lv + 1 v v ss_adc s r voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pin with respect to ground (v ss_hv ) ?v ss_hv ? 0.1 v ss_hv + 0.1 v table 10. recommended operating conditions (3.3 v) (continued) symbol parameter conditions value unit min max electrical characteristics spc564bxx-SPC56ECXX 56/123 docid17478 rev 9 v dd_hv_adc0 (5) s r voltage on vdd_hv_adc0 with respect to ground (v ss_hv ) ?4.55.5 v voltage drop (2) 3.0 5.5 relative to v dd_hv_a (6) v dd_hv_a ? 0.1 v dd_hv_a + 0.1 v dd_hv_adc1 (7) s r voltage on vdd_hv_adc1 with respect to ground (v ss_hv ) ?4.55.5 v voltage drop (2) 3.0 5.5 relative to v dd_hv_a (6) v dd_hv_a ?? 0.1 v dd_hv_a + 0.1 v in s r voltage on any gpio pin with respect to ground (v ss_hv ) ?v ss_hv ?0.1 ? v relative to v dd_hv_a/hv_b ? v dd_hv_a/hv_b + 0.1 i injpad s r injected input current on any pin during overload condition ??5 5 ma i injsum s r absolute sum of all injected input currents during overload condition ??50 50 tv dd s r v dd_hv_a slope to ensure correct power up (8) ??0.5v/s ?0.5 ?v/min t a c-grade part s r ambient temperature under bias ? ? 40 85 c t j c-grade part s r junction temperature under bias ? ? 40 110 t a v-grade part s r ambient temperature under bias ? ? 40 105 t j v-grade part s r junction temperature under bias ? ? 40 130 t a m-grade part s r ambient temperature under bias ? ? 40 125 t j m-grade part s r junction temperature under bias ? ? 40 150 1. 100 nf emi capacitance need to be provided between each vdd/vss_hv pair. 2. full device operation is guaranteed by des ign from 3.0 v?5.5 v. osc functionality is guaranteed from the entire range 3.0v?5.5 v, the parametrics measured are at 3.0v and 5.5v (e xtreme voltage ranges to cover the range of operation). the parametrics might have some variation in the intermediat e voltage range, but there is no impact to functionality. 3. 100 nf emi capacitance needs to be provided between each vdd_lv/vss_lv supply pair. 10 f bulk capacitance needs to be provided as creg on each vdd_lv pin. 4. this voltage is internally generated by t he device and no external voltage should be supplied. 5. 100 nf capacitance needs to be provided between v dd_hv_(adc0/adc1) /v ss_hv_(adc0/adc1) pair. 6. both the relative and the fixed conditions must be met. for instance: if v dd_hv_a is 5.9 v, v dd_hv_adc0 maximum value is 6.0 v then, despite the relative condition, the max value is v dd_hv_a + 0.3 = 6.2 v. 7. pa3, pa7, pa10, pa11 and pe12 adc_1 channels are coming from v dd_hv_b domain hence vdd_hv_adc1 should be within 100 mv of v dd_hv_b when these channels are used for adc_1. table 11. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max docid17478 rev 9 57/123 spc564bxx-SPC56ECXX electrical characteristics 122 note: sram retention guar anteed to lvd levels. 3.5 thermal characteristics 3.5.1 package thermal characteristics 8. guaranteed by device validation. table 12. lqfp thermal characteristics (1) symbol c parameter conditions (2) pin count value (3) unit min typ max r ? ja cc d thermal resistance, junction-to-ambient natural convection single-layer board?1s 176 ? ? 44.4 (4) c/w 208 ? ? 43 c/w r ? ja cc d thermal resistance, junction-to-ambient natural convection four-layer board?2s2p (5) 176 ? ? 36.1 c/w 208 ? ? 33.9 c/w 1. thermal characteristics are targets based on simulation that are subject to change per device characterization. 2. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c. 3. all values need to be conf irmed during device validation. 4. 1s board as per standard jedec (jesd51-7) in natural convection. 5. 2s2p board as per standard jedec (j esd51-7) in natural convection. table 13. lbga256 thermal characteristics (1) symbol c parameter conditions value unit r ? ja cc ? thermal resistance, junction-to-ambient natural convection single-layer board?1s 44.3 c/w four-layer board?2s2p 31 1. thermal characteristics are targets based on simulation that are subject to change per device characterization. electrical characteristics spc564bxx-SPC56ECXX 58/123 docid17478 rev 9 3.5.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : equation 1 t j = t a + (p d ? r ? ja ) where: t a is the ambient temperature in c. r ? ja is the package junction-to-ambient thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is confi gured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: equation 2 p d = k / (t j + 273 c) therefore, solving equations equation 1 and equation 2 : equation 3 k = p d ? (t a + 273 c) + r ? ja ? p d 2 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations equation 1 and equation 2 iteratively for any value of t a . 3.6 i/o pad electric al characteristics 3.6.1 i/o pad types the device provides four main i/o pad types depending on the associated alternate functions: ? slow pads?these pads are the most co mmon pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads?these pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. ? fast pads?these pads provide maximum s peed. these are used for improved nexus debugging capability. ? input only pads?these pads are associated to adc channels and 32 khz low power external crystal oscillator providing low input leakage. ? low power pads?these pads are active in standby mode for wakeup source. also, medium/slow and fast/medium pads are av ailable in design which can be configured to behave like a slow/medium and medium/fast pads depending upon the slew-rate control. docid17478 rev 9 59/123 spc564bxx-SPC56ECXX electrical characteristics 122 medium and fast pads can use slow configurat ion to reduce electromagnetic emission, at the cost of reducing ac performance. 3.6.2 i/o input dc characteristics table 14 provides input dc electrical characteristics as described in figure 5 . figure 5. i/o input dc electrical characteristics definition v il v in v ih pdix = ?1 v dd v hys (gpdi register of siul) pdix = ?0? table 14. i/o input dc electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65 v dd ?v dd + 0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.3 ? 0.35v dd v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? i lkg cc p digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 ? na pt a = 25 c ? 2 ? dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi sr p width of input pulse rejected by analog filter (3) ???40 (4) ns w nfi sr p width of input pulse accepted by analog filter (3) ?1000 (4) ??ns 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . all values need to be conf irmed during device validation. 3. analog filters are avai lable on all wakeup lines. electrical characteristics spc564bxx-SPC56ECXX 60/123 docid17478 rev 9 3.6.3 i/o output dc characteristics the following tables provide dc characteristics for bidirectional pads: ? table 15 provides weak pull figures. both pull-up and pull-down resistances are supported. ? table 16 provides output driver characte ristics for i/o pads when in slow configuration. ? table 17 provides output driver characteri stics for i/o pads when in medium configuration. ? table 18 provides output driver characte ristics for i/o pads when in fast configuration. 4. the width of input pulse in between 40 ns to 1000 ns is indeterminate. it may pass the noise or may not depending on silicon sample to sample variation. table 15. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions (1),(2) value unit min typ max |i wpu |cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 (3) 10 ? 250 p v in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 |i wpd |cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 p v in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are confi gured in input or in high impedance state. table 16. slow configuration output buffer electrical characteristics symbol c parameter conditions (1),(2) value unit min typ max v oh cc p output high level ? slow configuration push pull i oh = ? 3 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v c i oh = ? 3 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (3) 0.8v dd ?? p i oh = ? 1.5 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 v dd ?? 0.8 ? ? docid17478 rev 9 61/123 spc564bxx-SPC56ECXX electrical characteristics 122 v ol cc p output low level ? slow configuration push pull i ol = 3 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.1v dd v c i ol = 3 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (3) ? ? 0.1v dd p i ol = 1.5 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ??0.5 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are conf igured in input or in high impedance state. table 16. slow configuration output buffer electrical characteristics (continued) symbol c parameter conditions (1),(2) value unit min typ max table 17. medium configuration output buffer electrical characteristics symbol c parameter conditions (1) , (2) value unit min typ max v oh cc c output high level ? medium configuration push pull i oh = ? 3 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v c i oh = ? 1.5 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (3) 0.8v dd ?? c i oh = ? 2 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 v dd ?? 0.8 ? ? v ol cc c output low level ? medium configuration push pull i ol = 3 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.2v dd v c i ol = 1.5 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (3) ? ? 0.1v dd c i ol = 2 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ??0.5 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are confi gured in input or in high impedance state. electrical characteristics spc564bxx-SPC56ECXX 62/123 docid17478 rev 9 3.6.4 output pin transition times table 18. fast configuration output buffer electrical characteristics symbol c parameter conditions (1),(2) value unit min typ max v oh cc p output high level ? fast configuration push pull i oh = ? 14 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v c i oh = ? 7 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (3) 0.8v dd ?? c i oh = ? 11 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 v dd ?? 0.8 ? ? v ol cc p output low level ? fast configuration push pull i ol = 14 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.1v dd v c i ol = 7 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (3) ? ? 0.1v dd c i ol = 11 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ??0.5 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus outputs (mdox, evto, mcko) are configured in input or in high impedance state. table 19. output pin transition times symbol c parameter conditions (1),(2) value (3) unit min typ max t tr cc d output transition time output pin (4) ? slow configuration c l = 25 pf v dd = 5.0 v 10 %, ? pad3v5v = 0 ?? 50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10 %, pad3v5v = 1 ?? 40 tc l = 50 pf ? ? 50 dc l = 100 pf ? ? 75 t tr cc d output transition time output pin (4) ? medium configuration c l = 25 pf v dd = 5.0 v 10 %, pad3v5v = 0 siul.pcrx.src = 1 ?? 10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10 %, pad3v5v = 1 siul.pcrx.src = 1 ?? 12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 docid17478 rev 9 63/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.6.5 i/o pad current specification the i/o pads are distributed across the i/o supply segment. each i/o supply is associated to a v dd /v ss_hv supply pair as described in table 20 . table 21 provides i/o consumption figures. in order to ensure device reliability, the aver age current of the i/o on a single segment should remain below the i avgseg maximum value. in order to ensure device functionality, the sum of the dynamic and static current of the i/o on a single segment shou ld remain below the i dynseg maximum value. t tr cc d output transition time output pin (4) ? fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3. all values need to be confirmed during device validation. 4. c l includes device and package capacitances (c pkg < 5 pf). table 19. output pin transition times (continued) symbol c parameter conditions (1),(2) value (3) unit min typ max table 20. i/o supplies package i/o supplies lbga256 (1) equivalent to 208-pin lqfp segment pad distribution + g6, g11, h11, j11 lqfp208 pin6 (v dd_hv_a ) pin7 (v ss_hv ) pin27 (v dd_hv_a )pi n28 (v ss_hv ) pin73 (v ss_hv ) pin75 (v dd_hv_a ) pin101 (v dd_hv_a ) pin102 (v ss_hv ) pin132 (v ss_hv ) pin133 (v dd_hv_a ) pin147 (v ss_hv ) pin148 (v dd_hv_b ) pin174 (v ss_hv ) pin175 (v dd_hv_a ) ? lqfp176 pin6 (v dd_hv_a ) pin7 (v ss_hv ) pin27 (v dd_hv_a )pi n28 (v ss_hv ) pin57 (v ss_hv ) pin59 (v dd_hv_a ) pin85 (v dd_hv_a ) pin86 (v ss_hv ) pin123 (v ss_hv ) pin124 (v dd_hv_b ) pin150 (v ss_hv ) pin151 (v dd_hv_a ) ?? 1. vdd_hv_b supplies the io voltage domain for the pins pe[12 ], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg[0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], and pa[3]. electrical characteristics spc564bxx-SPC56ECXX 64/123 docid17478 rev 9 table 21. i/o consumption symbol c parameter conditions (1),(2) value (3) unit min typ max i swtslw (4) c c d peak i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, ? pad3v5v = 0 ? ? 19.9 ma v dd = 3.3 v 10%, ? pad3v5v = 1 ? ? 15.5 i swtmed (4) c c d peak i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, ? pad3v5v = 0 ? ? 28.8 ma v dd = 3.3 v 10%, ? pad3v5v = 1 ? ? 16.3 i swtfst (4) c c d peak i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, ? pad3v5v = 0 ? ? 113.5 ma v dd = 3.3 v 10%, ? pad3v5v = 1 ? ? 52.1 i rmsslw c c d root mean square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, ? pad3v5v = 0 ? ? 2.22 ma c l = 25 pf, 4 mhz ? ? 3.13 c l = 100 pf, 2 mhz ? ? 6.54 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, ? pad3v5v = 1 ? ? 1.51 c l = 25 pf, 4 mhz ? ? 2.14 c l = 100 pf, 2 mhz ? ? 4.33 i rmsmed c c d root mean square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.5 ma c l = 25 pf, 40 mhz ? ? 13.32 c l = 100 pf, 13 mhz ? ? 18.26 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ? ? 4.91 c l = 25 pf, 40 mhz ? ? 8.47 c l = 100 pf, 13 mhz ? ? 10.94 i rmsfst c c d root mean square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??21.05 ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 55.77 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 34.89 i avgseg s r d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 (4) 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3. all values need to be conf irmed during device validation. 4. stated maximum values represent peak consumpti on that lasts only a few ns during i/o transition. docid17478 rev 9 65/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.7 reset electrical characteristics the device implements a dedicated bidirectional reset pin. figure 6. start-up reset requirements figure 7. noise filtering on reset signal v il v dd_hv_a device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset electrical characteristics spc564bxx-SPC56ECXX 66/123 docid17478 rev 9 table 22. reset electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max v ih s r p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd + 0.4 v v il s r p input low level cmos (schmitt trigger) ? ? 0.3 ? 0.35v dd v v hys c c c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol c c p output low level push pull, i ol = 2 ma, ? v dd = 5.0 v 10 %, pad3v5v = 0 ? (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (3) ? ? 0.1v dd push pull, i ol = 1 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ?? 0.5 t tr c c d output transition time output pin (4) ? medium configuration c l = 25 pf, ? v dd = 5.0 v 10%, pad3v5v = 0 ?? 10 ns c l = 50 pf, ? v dd = 5.0 v 10%, pad3v5v = 0 ?? 20 c l = 100 pf, ? v dd = 5.0 v 10%, pad3v5v = 0 ?? 40 c l = 25 pf, ? v dd = 3.3 v 10%, pad3v5v = 1 ?? 12 c l = 50 pf, ? v dd = 3.3 v 10%, pad3v5v = 1 ?? 25 c l = 100 pf, ? v dd = 3.3 v 10%, pad3v5v = 1 ?? 40 w frst s r p reset input filtered pulse ???40ns w nfrs t s r p reset input not filtered pulse ? 1000 ? ? ns |i wpu | c c p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 (5) 10 ? 250 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . all values need to be conf irmed during device validation. 3. this is a transient configuration duri ng power-up, up to the end of reset phase2 (refer to the rgm module section of the device reference manual). 4. c l includes device and package capacitance (c pkg < 5 pf). 5. the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. docid17478 rev 9 67/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.8 power management el ectrical characteristics 3.8.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage supply v dd_hv_a . the following supp lies are involved: ? hv: high voltage external power supply for voltage regulator module. this must be provided externally through v dd_hv_a power pin. ? lv: low voltage internal power supply for core, fmpll and flash digital logic. this is generated by the on-chip vreg with an external ballast (bcp68 npn device). it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla0/cfla1: low voltage supply fo r the two code flash modules. it is shorted with lv_cor through double bonding. ? lv_dfla: low voltage supply for data flash module. it is shorted with lv_cor through double bonding. ? lv_pll: low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 8. voltage regula tor capacitance connection 32 kb 56 kb split split ctrl ctrl split ctrl pd0 (always on domain) pd1 switchable domain hpreg lpreg hpvdd lpvdd vdd_lv vss_lv off chip bcp68 40 ? f hpvdd lpvdd sw1 (<0.1 ? ) 8kb pd0 logic vdd_bv vdd_hv_a vss_hv 100 nf (fmpll, flash) vdd_lv vdd_lv vdd_lv vss_lv vss_lv vss_lv 100 nf 100 nf 100 nf vrc_ctrl (c regn ) chip boundary 10 ? f (c dec2 ) (4 ? 10 ? f) npn driver 1) all vss_lv pins must be grounded, as shown for vss_hv pin. electrical characteristics spc564bxx-SPC56ECXX 68/123 docid17478 rev 9 the internal voltage regulator requires external bulk capacitance (c regn ) to be connected to the device to provide a stable low voltage digital supply to the device. also required for stability is the c dec2 capacitor at ballast collector. this is needed to minimize sharp injection current when ballast is turning on. apart from the bulk capacitance, user should connect emi/decoupling cap (c regp ) at each v dd_lv /v ss_lv pin pair. 3.8.1.1 recommendations ? the external npn driver must be bcp68 type. ? v dd_lv should be implemented as a power plane from the emitter of the ballast transistor. ? 10 ? f capacitors should be connected to the 4 pins cl osest to the outside of the package and should be evenly distributed around the package. for bga packages, the balls should be used are d8, h14, r9, j3?one cap on each side of package. ? there should be a track direct from the capacitor to this pin (pin also connects to v dd_lv plane). the tracks esr should be less than 100 m ? . ? the remaining v dd_lv pins (exact number will va ry with package) should be decoupled with 0.1 ? f caps, connected to the pin as per 10 ? f. (see section 3.4: recommended operating conditions ). 3.8.2 v dd_bv options ? option 1: v dd_bv shared with v dd_hv_a v dd_bv must be star routed from v dd_hv_a from the common so urce. this is to eliminate ballast noise injection on the mcu. ? option 2: v dd_bv independent of the mcu supply v dd_bv > 2.6 v for correct functionality. the dev ice is not monitoring this supply hence the external component must meet the 2.6 v criteria through external monitoring if required. table 23. voltage regulator electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max c regn s r ? external ballast stability capacitance ?40?60 ? f r reg s r ? stability capacitor equivalent serial resistance ???0.2w c regp s r ? decoupling capacitance (close to the pin) v dd_hv_a/hv_b /v ss_hv pair 100 ? nf v dd_lv /v ss_lv pair 100 ? nf c dec2 s r ? stability capacitance regulator supply (close to the ballast collector) v dd_bv /v ss_hv 10 ? 40 ? f v mreg c c p main regulator output voltage after trimming t a = 25 c 1.20 1.28 1.32 v docid17478 rev 9 69/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.8.3 voltage monitor el ectrical characteristics the device implements a power-on reset module to ensure correct po wer-up initialization, as well as four low voltage detectors to monitor the v dd_hv_a and the v dd_lv voltage while device is supplied: ? por monitors v dd_hv_a during the power-up phase to ensure device is maintained in a safe reset state ? lvdhv3 monitors v dd_hv_a to ensure device is rese t below minimum functional supply ? lvdhv5 monitors v dd_hv_a when application uses device in the 5.0 v10 % range ? lvdlvcor monitors powe r domain no. 1 (pd1) ? lvdlvbkp monitors power doma in no. 0 (pd0). vdd_lv is same as pd0 supply. note: when enabled, pd2 (ram retention) is monitored through lvd_digbkp. i mreg s r ? main regulator current provided to v dd_lv domain ??? 350 ma i mregint c c d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg c c p low power regulator output voltage after trimming t a = 25 c 1.17 1.27 1.32 v i lpreg s r ? low power regulator current provided to v dd_lv domain ? ?? 50 ma i lpregint c c d low power regulator module current consumption i lpreg = 15 ma; ? t a = 55 c ?? 600 ? a ? i lpreg = 0 ma; ? t a = 55 c ? 20 ? i vregref c c d main lvds and reference current consumption (low power and main regulator switched off) t a = 55 c ? 2 ? ? a i vredlvd12 c c d main lvd current consumption (switch-off during standby) t a = 55 c ? 1 ? ? a i dd_hv_a c c d in-rush current on v dd_bv during power-up ?? ? 600 (3) ma 1. v dd_hv_a = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. all values need to be conf irmed during device validation. 3. inrush current is seen more like steps of 600 ma peak. the startup of the regulator happens in steps of 50 mv in ~25 steps to reach ~1.2 v v dd_lv . each step peak current is within 600 ma table 23. voltage regulator electrical characteristics (continued) symbol c parameter conditions (1) value (2) unit min typ max electrical characteristics spc564bxx-SPC56ECXX 70/123 docid17478 rev 9 figure 9. low voltage monitor vs. reset 3.9 low voltage domain power consumption table 25 provides dc electrical characteristic s for significant application modes. these values are indicative values; actual consumption depends on the application. v ddhv/lv v lvdhvxh/lvxh reset v lvdhvxl/lvxl table 24. low voltage monitor electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max v porup s r p supply for functional por module ? 1.0 ? 5.5 v v porh c c p power-on reset threshold ? 1.5 ? 2.6 v lvdhv3h c c t lvdhv3 low voltage detector high threshold ? 2.7 ? 2.85 v lvdhv3l c c t lvdhv3 low voltage detector low threshold ? 2.6 ? 2.74 v lvdhv5h c c t lvdhv5 low voltage detector high threshold ? 4.3 ? 4.5 v lvdhv5l c c t lvdhv5 low voltage detector low threshold ? 4.2 ? 4.4 v lvdlvcorl c c p lvdlvcor low voltage detector low threshold t a = 25 c, after trimming 1.08 ? 1.17 v lvdlvbkpl c c p lvdlvbkp low voltage detect or low threshold 1.08 ? 1.17 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. all values need to be conf irmed during device validation. docid17478 rev 9 71/123 spc564bxx-SPC56ECXX electrical characteristics 122 table 25. low voltage power domai n electrical characteristics (1) symbol c parameter conditions (2) value unit min typ (3) max (4) i ddmax (5) c c d run mode maximum average current ? ? 210 300 (6), (7) ma i ddrun c c p run mode typical average current (8) at 120 mhz t a = 25 c ? 150 208 (9) ma dat 80 mhzt a = 25 c ? 110 (8) 150 (10) ma c at 120 mhz t a = 125 c ? 180 280 ma i ddhalt c c p halt mode current (11) at 120 mhz t a = 25 c ? 20 27 ma c at 120 mhz t a = 125 c ? 35 100 ma i ddstop c c p stop mode current (12) no clocks active t a = 25 c ? 0.4 5 ma ct a = 125 c ? 16 72 ma i ddstdby3 (96 kb ram retained) c c p standby3 mode current (13) no clocks active t a = 25 c ? 50 96 a ct a = 125 c ? 630 2400 a i ddstdby2 (64 kb ram retained) c c c standby2 mode current (14) no clocks active t a = 25 c ? 40 92 a ct a = 125 c ? 500 2000 a i ddstdby1 (8 kb ram retained) c c c standby1 mode current (15) no clocks active t a = 25 c ? 25 85 a ct a = 125 c ? 230 1100 a adders in lp mode c c t 32 khz osc ? t a = 25 c ? ? 5 a 4?40 mhz osc ? t a = 25 c ? ? 3 ma 16 mhz irc ? t a = 25 c ? ? 500 a 128 khz irc ? t a = 25 c ? ? 5 a 1. except for i ddmax , all the current values are total current drawn from v dd_hv_a . 2. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified all temperatures are based on an ambient temperature. 3. target typical current consumption for the following typica l operating conditions and confi guration. process = typical, voltage = 1.2 v. 4. target maximum current consumption for mode observed un der typical operating conditions . process = fast, voltage = 1.32 v. 5. running consumption is given on voltage regulator supply (v ddreg ). it does not include cons umption linked to i/os toggling. this value is highly dependent on the application. the gi ven value is thought to be a worst case value with all cores and peripherals running, and code fetched from code flash while modify operati on on-going on data flash. it is to be noticed that this value can be significan tly reduced by applicati on: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from ram most used functions, use low power mode when possible. 6. higher current may sunk by device during power-up and standby exit. please refer to in rush current in table 23 . 7. maximum ?allowed? current is package dependent. 8. only for the ?p? classification: code fetched from ram: serial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x multiplier) peripherals on (emios/c tu/adc) and running at max frequency, periodic sw/wdg timer reset enabled. run current measured with typical a pplication with accesses on both code flash and ram. electrical characteristics spc564bxx-SPC56ECXX 72/123 docid17478 rev 9 3.10 flash memory elect rical characteristics 3.10.1 program/erase characteristics table 26 shows the code flash memory pr ogram and erase characteristics. table 27 shows the data flash memory program and erase characteristics. 9. subject to change, configuration: 1 ?? e200z4d + 4 kbit/s cache, 1 ?? e200z0h (1/2 system frequency), cse, 1 ?? e dma (10 ch.), 6 ?? flexcan (4 ?? 500 kbit/s, 2 ?? 125 kbit/s), 4 ?? linflexd (20 kbit/s), 6 ?? dspi (2 ?? 2 mbit/s, 3 ?? 4 mbit/s, 1 ?? 10 mbit/s), 16 ?? timed i/o, 16 ?? adc input, 1 ?? flexray (2 ch., 10 mbit/s), 1 ?? fec (100 mbit/s), 1 ?? rtc, 4 ? pit channels, 1 ?? swt, 1 ?? stm. for lower pin count packages reduce th e amount of timed i/o?s and adc channels. run current measured with typical application with accesses on both code flash and ram. 10. this value is obtained from limited sample set. 11. data flash power down. code flash in low power. sirc 128 khz and firc 16 mhz on. 16 mhz xtal clock. flexcan: instances: 0, 1, 2 on (clocked but no rec eption or transmission), instances: 4, 5, 6 clocks gated. linflex: instances: 0, 1, 2 on (clocked but no reception or transmission), instance: 3-9 clocks gated. emios: instance: 0 on (16 channels on pa[0]- pa[11] and pc[12]-pc[15]) with pwm 20 khz, instance: 1 cl ock gated. dspi: instance: 0 (clocked but no communication, instance: 1-7 clocks gated). rtc/api on. pit on. stm on. adc on but no conversion except 2 analog watchdogs. 12. only for the ?p? classifica tion: no clock, firc 16 mhz off, sirc128 khz on, pll off, hpvreg off, lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 13. only for the ?p? classifica tion: lpreg on, hpvreg off, 96 kb ram on, devi ce configured for mini mum consumption, all possible modules switched-off. measurement condition assumes t j = ta. 14. lpreg on, hpvreg off, 64 kb ram on, device configured for minimum consumption, all pos sible modules switched-off. measurement condition assumes t j = ta. 15. lpreg on, hpvreg off, 8 kb ram on, device configured for minimum consumption, all pos sible modules switched off. measurement condition assumes t j = ta. table 26. code flash memory?program and erase specifications symbol c parameter value unit min typ (1) initial max (2) max (3) t dwprogram c c c double word (64 bits) program time (4) ? 18 50 500 s t 16kpperase 16 kb block pre-program and erase time ? 200 500 5000 ms t 32kpperase 32 kb block pre-program and erase time ? 300 600 5000 ms t 128kpperase 128 kb block pre-program and erase time ? 600 1300 5000 ms t eslat d erase suspend latency ? ? 30 30 s t esrt (5) c erase suspend request rate 20 ? ? ? ms t pabt d program abort latency ? ? 10 10 s t eapt d erase abort latency ? ? 30 30 s 1. typical program and erase times assume nominal supply va lues and operation at 25 c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/e rase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occur after the specif ied number of program/erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. this does not include software overhead. 5. it is time between erase suspend re sume and the next erase suspend request. docid17478 rev 9 73/123 spc564bxx-SPC56ECXX electrical characteristics 122 table 27. data flash memory?program and erase specifications symbol c parameter value unit min typ (1) initial max (2) max (3) t wprogram c c c word (32 bits) program time (4) ? 30 70 500 s t 16kpperase 16 kb block pre-program and erase time ? 700 800 5000 ms t eslat d erase suspend latency ? ? 30 30 s t esrt (5) c erase suspend request rate 10 ? ? ? ms t pabt d program abort latency ? ? 12 12 s t eapt d erase abort latency ? ? 30 30 s 1. typical program and erase times assume nominal supply va lues and operation at 25 c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/e rase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occur after the specif ied number of program/erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. this does not include software overhead. 5. it is time between erase suspend resume and next erase suspend. table 28. flash memory module life symbol c parameter conditions value unit min typ p/e cc c number of program/erase cycles per block for 16 kbyte blocks over the operating temperature range (t j ) ? 100000 100000 cycles number of program/erase cycles per block for 32 kbyte blocks over the operating temperature range (t j ) ? 10000 100000 cycles number of program/erase cycles per block for 128 kbyte blocks over the operating temperature range (t j ) ? 1000 100000 cycles retention cc c minimum data retention at 85 c average ambient temperature (1) blocks with 0?1000 p/e cycles 20 ? years blocks with 10000 p/e cycles 10 ? years blocks with 100000 p/e cycles 5 ? years 1. ambient temperature averaged over dur ation of application, not to exceed recommended product operating temperature range. electrical characteristics spc564bxx-SPC56ECXX 74/123 docid17478 rev 9 ecc circuitry provides correction of single bit faults and is used to improve further automotive reliability re sults. some units will experience si ngle bit correc tions throughout the life of the product with no impact to product reliability. 3.10.2 flash memory power supply dc characteristics table 30 shows the flash memory power supply dc characteristics on external supply. table 29. flash memory read access timing (1) symbol c parameter conditions (2) frequency range unit code flash memory data flash memory f read cc p maximum frequency for flash reading 5 wait states 13 wait states 120 ?100 mhz c 4 wait states 11 wait states 100?80 d 3 wait states 9 wait states 80?64 c 2 wait states 7 wait states 64?40 c 1 wait states 4 wait states 40?20 c 0 wait states 2 wait states 20?0 1. max speed is the maximum speed allowed including pll frequency modulation (fm). 2. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. table 30. flash memory power supply dc electrical characteristics symbol parameter conditions (1) value (2) unit min typ max i cfread (3) c c sum of the current consumption on v dd_hv_a on read access flash memory module read ? f cpu = 120 mhz ? 2% (4) code flash memory 33 ma i dfread (3) data flash memory 13 i cfmod (3) c c sum of the current consumption on v dd_hv_a (program/erase) program/erase on-going while reading flash memory registers ? f cpu = 120 mhz ? 2% (4) code flash memory 52 ma i dfmod (3) data flash memory 13 i cflpw (3) c c sum of the current consumption on v dd_hv_a during flash memory low power mode code flash memory 1.1 ma i cfpwd (3) c c sum of the current consumption on v dd_hv_a during flash memory power down mode code flash memory 150 a i dfpwd (3) data flash memory 150 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ?40 to 125 c, unless otherwise specified. 2. all values need to be confirmed during device validation. 3. data based on characterization results, not tested in production. 4. f cpu 120 mhz ? 2 % can be achieved over full temperatur e 125 c ambient, 150 c junction temperature. docid17478 rev 9 75/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.10.3 flash memory st art-up/switch-off timings 3.11 electromagnetic compati bility (emc) characteristics susceptibility tests are perfor med on a sample basis during product characterization. 3.11.1 designing hardened soft ware to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and pre- qualification tests in relation with the emc level requested for the application. ? software recommendations ?? the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers) ? pre-qualification trials ?? most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note software techniques for improving microcontroller emc performance (an1015)). table 31. start-up time/switch-off time symbol c parameter conditions (1) value unit min typ max t flarstexit c c d delay for flash memory module to exit reset mode code flash memory ? ?? 125 s data flash memory ?? t flalpexit c c t delay for flash memory module to exit low-power mode code flash memory ???0.5 t flapdexit c c t delay for flash memory module to exit power-down mode code flash memory ? ?? 30 data flash memory ?? t flalpentr y c c t delay for flash memory module to enter low-power mode code flash memory ???0.5 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. electrical characteristics spc564bxx-SPC56ECXX 76/123 docid17478 rev 9 3.11.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec61967-1 standard, wh ich specifies the genera l conditions for emi measurements. 3.11.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 3.11.3.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts ? ? (n+1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. for more details, refer to the application note electrostatic discharge sensitivity measurement (an1181). table 32. emi radiated emission measurement (1)(2) symbol c parameter conditions value unit min typ max ? s r ? scan range ? 0.150 1000 mhz f cpu s r ? operating frequency ??120?mhz v dd_lv s r ? lv operating voltages ? ? 1.28 ? v s emi c c t peak level v dd = 5 v, t a = 25 c, ? lqfp176 package ? test conforming to iec 61967-2, ? f osc = 40 mhz/f cpu = 120 mhz no pll frequency modulation ? ? 18 dbv 2% pll frequency ? modulation ??14 (3) dbv 1. emi testing and i/o port waveforms per iec 61967-1, -2, -4. 2. for information on conducted emission and susceptibility measurement (norm ie c 61967-4), please contact your local marketing representative. 3. all values need to be conf irmed during device validation. table 33. esd absolute maximum ratings (1)(2) symbol ratings conditions class max value (3) unit v esd(hbm) electrostatic discharge voltage ? (human body model) t a = 25 c ? conforming to aec-q100-002 h1c 2000 v v esd(mm) electrostatic discharge voltage ? (machine model) t a = 25 c ? conforming to aec-q100-003 m2 200 v esd(cdm) electrostatic discharge voltage ? (charged device model) t a = 25 c ? conforming to aec-q100-011 c3a 500 750 (corners) docid17478 rev 9 77/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.11.3.2 static latch-up (lu) two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply over-voltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.12 fast external crystal osc illator (4?40 mhz) electrical characteristics the device provides an o scillator/resona tor driver. figure 10 describes a simple model of the internal oscillator driver and provides an example of a co nnection for an oscillator or a resonator. table 35 provides the parameter description of 4 mhz to 40 mhz crystals used for the design simulations. 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional test ing shall be performed per applic able device specification at room temperature followed by hot temperature, unles s specified otherwise in the device specification. 3. data based on characterization re sults, not tested in production. table 34. latch-up results symbol parameter conditions class lu static latch-up class t a = 125 c ? conforming to jesd 78 ii level a electrical characteristics spc564bxx-SPC56ECXX 78/123 docid17478 rev 9 figure 10. crystal oscillator and resonator connection scheme note: xtal/extal must not be directly used to drive external circuits. c2 c1 crystal xtal extal resonator xtal extal device device device extal xtal i r v dd r d table 35. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) (1) shunt capacitance between xtalout and xtalin c0 (2) (pf) 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 40 nx5032ga 50 6.18 2.56 8 3.49 1. the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc. ) as the ac / transient behavior depends upon them. 2. the value of c0 specified here includes 2 pf additional ca pacitance for parasitics (to be seen with bond-pads, package, etc.). docid17478 rev 9 79/123 spc564bxx-SPC56ECXX electrical characteristics 122 figure 11. fast external crystal oscillator (4 to 40 mhz) electrical characteristics v fxoscop t mxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f mxosc s_mtrans bit (me_gs register) 1 0 table 36. fast external crystal oscillator (4 to 40 mhz) electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max f fxosc sr ? fast external crystal oscillator frequency ?4.0?40.0mhz g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10% 4 (3) ?20 (3) ma/v v dd = 5.0 v 10% 6.5 (3) ?25 (3) v fxosc cc t oscillation amplitude at extal f osc = 40 mhz for both v dd = 3.3 v 10%, v dd = 5.0 v 10% ?0.95 ? v v fxoscop cc p oscillation operating point ??1.8 v i fxosc (4) cc t fast external crystal oscillator consumption v dd = 3.3 v 10%, f osc = 40 mhz ?2 2.2 ma v dd = 5.0 v 10%, f osc = 40 mhz ?2.3 2.5 v dd = 3.3 v 10%, f osc = 16 mhz ?1.3 1.5 v dd = 5.0 v 10%, f osc = 16 mhz ?1.6 1.8 t fxoscsu cc t fast external crystal oscillator start-up time f osc = 40 mhz for both v dd = 3.3 v 10%, v dd = 5.0 v 10% ?? 5 ms electrical characteristics spc564bxx-SPC56ECXX 80/123 docid17478 rev 9 3.13 slow external crystal osc illator (32 khz) electrical characteristics the device provides a low powe r oscillator/reso nator driver. figure 12. crystal oscillator and resonator connection scheme note: osc32k_xtal/osc32k_extal must not be directly used to drive external circuits. l v ih sr p input high level cmos ? (schmitt trigger) oscillator bypass mode 0.65v dd_ hv_a ?v dd_hv_a + 0.4 v v il sr p input low level cmos ? (schmitt trigger) oscillator bypass mode ? 0.3 ? 0.35v dd_hv_a v 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. all values need to be confir med during device validation. 3. based on ate cz 4. stated values take into account onl y analog module consumption but not the di gital contributor (clock tree and enabled peripherals). table 36. fast external crystal oscillator (4 to 40 mhz) electrical characteristics (continued) symbol c parameter conditions (1) value (2) unit min typ max osc32k_xtal osc32k_extal device c2 c1 crystal osc32k_xtal osc32k_extal r p resonator device docid17478 rev 9 81/123 spc564bxx-SPC56ECXX electrical characteristics 122 figure 13. equivalent circuit of a quartz crystal c0 c2 c1 c2 r m c1 l m c m crystal table 37. crystal motional characteristics (1) symbol parameter conditions value unit min typ max l m motional inductance ? ? 11.796 ? kh c m motional capacitance ? ? 2 ? ff c1/c2 load capacitance at osc32k_xtal and osc32k_extal with respect to ground (2) ?18?28pf r m (3) motional resistance ac coupled @ c0 = 2.85 pf (4) ??65 kw ac coupled @ c0 = 4.9 pf (4) ??50 ac coupled @ c0 = 7.0 pf (4) ??35 ac coupled @ c0 = 9.0 pf (4) ??30 1. the crystal used is epson toyocom mc306. 2. this is the recommended range of load capacitance at os c32k_xtal and osc32k_extal with respect to ground. it includes all the parasitics due to board traces, crystal and package. 3. maximum esr (r m ) of the crystal is 50 k ?? 4. c0 includes a parasitic capacitance of 2.0 pf between osc32k_xtal and osc32k_extal pins. electrical characteristics spc564bxx-SPC56ECXX 82/123 docid17478 rev 9 figure 14. slow external crystal oscill ator (32 khz) electrical characteristics oscon bit (osc_ctl register) t lpxosc32ksu 1 v osc32k_xtal v lpxosc32k valid internal clock 90% 10% 1/f lpxosc32k 0 table 38. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max f sxosc s r ? slow external crystal oscillator frequency ?32 32.76 8 40 khz g msxosc c c ? slow external crystal oscillator transconductance v dd = 3.3 v 10%, 13 (3) ?33 (3) a/v v dd = 5.0 v 10% 15 (3) ?35 (3) v sxosc c c t oscillation amplitude ? 1.2 1.4 1.7 v i sxoscbias c c t oscillation bias current ? 1.2 ? 4.4 a i sxosc c c t slow external crystal oscillator consumption ???7a t sxoscsu c c t slow external crystal oscillator start-up time ???2 (4) s 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. all values need to be conf irmed during device validation. 3. based on ate cz 4. start-up time has been measured with epson toyocom mc 306 crystal. variation may be seen with other crystal. docid17478 rev 9 83/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.14 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmpll) module to generate a fast system clock fr om the main os cillator driver. 3.15 fast internal rc o scillator (16 mhz) electr ical characteristics the device provides a 16 mhz main internal rc oscillator. this is used as the default clock at the power-up of the device and can also be used as input to pll. table 39. fmpll electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max f pllin s r ? fmpll reference clock (3) ?4?64mhz ? pllin s r ? fmpll reference clock duty cycle (3) ?40?60% f pllout c c p fmpll output clock frequency ? 16 ? 120 mhz f cpu s r ? system clock frequency ? ? ? 120 + 2% (4) mhz f free c c p free-running frequency ? 20 ? 150 mhz t lock c c p fmpll lock time stable oscillator (f pllin = 16 mhz) 40 100 s ? t ltjit c c ? fmpll long term jitter f pllin = 40 mhz (resonator) , f pllclk @ 120 mhz, 4000 cycles ?? 6 (for < 1ppm) ns i pll c c c fmpll consumption t a = 25 c ? ? 3 ma 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. all values need to be conf irmed during device validation. 3. pllin clock retrieved directly from 4-40 mhz xosc or 16 mirc. input characteri stics are granted when oscillator is used in functional mode. when bypass mode is us ed, oscillator input clock should verify f pllin and ? pllin . 4. f cpu 120 + 2% mhz can be achieved at 125 c. table 40. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max f firc c c p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz s r ??1220 electrical characteristics spc564bxx-SPC56ECXX 84/123 docid17478 rev 9 i fircrun (3) c c t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a i fircpwd c c d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? 100 na dt a = 55 c ? ? 200 na dt a = 125 c ? ? 1 a i fircstop c c t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ? 1250 ? t fircsu c c c fast internal rc oscillator start-up time t a = 55 c v dd = 5.0 v 10% ??2.0 s ? v dd = 3.3 v 10% ??5 ? t a = 125 c v dd = 5.0 v 10% ??2.0 ? v dd = 3.3 v 10% ??5 ? fircpre c c c fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1?+1% ? firctrim c c c fast internal rc oscillator trimming step t a = 25 c ? 1.6 % ? fircvar c c c fast internal rc oscillator variation over temperature and supply with respect to f firc at t a = 25 c in high-frequency configuration ? ? 5?+5% 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. all values need to be conf irmed during device validation. 3. this does not include consumpt ion linked to clock tree toggling and peripher als consumption when rc oscillator is on. table 40. fast internal rc oscillator (16 mhz) electrical characteristics (continued) symbol c parameter conditions (1) value (2) unit min typ max docid17478 rev 9 85/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.16 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz low power internal rc oscillator. this can be used as the reference clock for the rtc module. 3.17 adc electrical characteristics 3.17.1 introduction the device provides two successive approx imation register (sar) analog-to-digital converters (10-bit and 12-bit). note: due to adc limitations, the two adcs cannot sample a shared channel at the same time i.e., their sampling windows cannot overlap if a shared channel is selected. if this is done, neither of the adcs can guaran tee their conversion accuracies. table 41. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions (1) value (2) unit min typ max f sirc c c p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz s r ? untrimmed, across temperatures 84 ? 205 i sirc (3) c c c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu c c p slow internal rc oscillator start- up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s ? sircpre c c c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2?+2 % ? sirctrim c c c slow internal rc oscillator trimming step ??2.7? ? sircvar c c c variation in f sirc across temperature and fluctuation in supply voltage, post trimming ? ? 10 ? +10 % 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. all values need to be conf irmed during device validation. 3. this does not include consumpt ion linked to clock tree toggling and peripher als consumption when rc oscillator is on. electrical characteristics spc564bxx-SPC56ECXX 86/123 docid17478 rev 9 figure 15. adc_0 characteristic and error definitions 3.17.1.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device, can be effective: the capaci tor should be as large as possible, ideally infinite. this capacitor contri butes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. a real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filt ering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal ( bandwidth) and the equivalent input impedance of the adc itself. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve ( 2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = vdd_adc / 1024 docid17478 rev 9 87/123 spc564bxx-SPC56ECXX electrical characteristics 122 in fact a current sink contributor is repres ented by the charge sharing effects with the sampling capacitance: being cs and cp 2 substantially two switched capacitances, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1mhz, with cs+cp 2 equal to 3pf, a resistance of 330k ? is obtained (reqiv = 1 / (fc*(cs+cp 2 )), where fc represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on cs+cp 2 ) and the sum of r s + r f , the external circuit must be desi gned to respect the following relation equation 4 the formula above provides a constraint for external network design, in particular on resistive path. figure 16. input equivalent ci rcuit (precise channels) v a r s r f + r eq --------------------- ? 1 2 -- -lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a electrical characteristics spc564bxx-SPC56ECXX 88/123 docid17478 rev 9 figure 17. input equivalent circuit (extended channels) a second aspect involving the capacitance network shall be c onsidered. assuming the three capacitances c f , c p1 and c p2 initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 16 ): when the sampling phase is started (a/d switch close), a charge sharing phenomena is installed. figure 18. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially co mpletely discharged): considering a worst case (since the time co nstant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? docid17478 rev 9 89/123 spc564bxx-SPC56ECXX electrical characteristics 122 this relation can again be simplified considering c s as an additional worst condition. in reality, transient is faster, but the a/d converter circuitry has been designed to be robust also in very worst case: the sampling time t s is always much longer than the internal time constant. equation 6 the charge of c p1 and c p2 is redistributed on c s ,determining a new value of the voltage v a1 on the capacitance according to the following equation equation 7 a second charge transf er involves also c f (that is typically bigger than the on-chip capacitance) through the resistance rl: again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in re ality would be faster), the time constant is: equation 8 in this case, the time constant depends on the ex ternal circuit: in partic ular imposing that the transient is complete d well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be mu ch higher than v a1 . the following equation must be respected (charge balance assuming now c s already charged at v a1 ): equation 10 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically de signed to act as anti-aliasing ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? ? 2 ? 8.5 r l c s c p1 c p2 ++ ?? ? ? =t s ? v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = electrical characteristics spc564bxx-SPC56ECXX 90/123 docid17478 rev 9 figure 19. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the f ilter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific chan nel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by t he analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 12 adc_0 (10-bit) equation 13 adc_1 (12-bit) f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise v a2 v a ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ? c f 8192 c s ? ? docid17478 rev 9 91/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.17.1.2 adc electrical characteristics table 42. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc c input leakage current t a = ? 40 c no current injection on adjacent pin ?1? na ct a = 25 c ? 1 ? ct a = 105 c ? 8 200 pt a = 125 c ? 45 400 table 43. adc conversion characteristics (10-bit adc_0) symbol c parameter conditions (1) value unit min typ max v ss_adc0 s r ? voltage on vss_hv_adc0 (adc_0 reference) pin with respect to ground (v ss_hv ) (2) ? ? 0.1 ? 0.1 v v dd_adc0 s r ? voltage on vdd_hv_adc0 pin (adc_0 reference) with respect to ground (v ss_hv ) ?v dd_hv_a ?? 0.1 ? v dd_hv_a + 0.1 v v ainx s r ? analog input voltage (3) ?v ss_adc0 ?? 0.1 ? v dd_adc0 + 0.1 v f adc0 s r ? adc_0 analog frequency ? 6? 32 + 2% mhz t adc0_pu s r ? adc_0 power up delay ? ?? 1.5 s t adc0_s c c t sample time (4) f adc = 32 mhz 500 ? ns t adc0_c c c p conversion time (5),(6) f adc = 32 mhz 0.625 ? s f adc = 30 mhz 0.700 ? c s c c d adc_0 input sampling capacitance ??? 3 pf c p1 c c d adc_0 input pin capacitance 1 ??? 3 pf c p2 c c d adc_0 input pin capacitance 2 ??? 1 pf c p3 c c d adc_0 input pin capacitance 3 ??? 1 pf r sw1 c c d internal resistance of analog source ??? 3 k ? electrical characteristics spc564bxx-SPC56ECXX 92/123 docid17478 rev 9 r sw2 c c d internal resistance of analog source ? ? ? 2 k ? r ad c c d internal resistance of analog source ??? 2 k ? i inj (7) s r ? input current injection current injectio n on one adc_0 input, differen t from the convert ed one v dd = ? 3.3 v 10% ? 5? 5 ma v dd = ? 5.0 v 10% ? 5 ? 5 | inl | c c t absolute value for integral non-linearity no overload ? 0.5 1.5 lsb | dnl | c c t absolute differential non-linearity no overload ? 0.5 1.0 lsb | ofs | c c t absolute offset error ? ? 0.5 ? lsb | gne | c c t absolute gain error ?? 0.6 ? lsb tuep c c p total unadjusted error (8) for precise channels, input only pins without current injection ? 2 0.6 2 lsb t with current injection ? 3 3 tuex c c t total unadjusted error (8) for extended channel without current injection ? 3 1 3 lsb t with current injection ? 4 4 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. analog and digital v ss_hv must be common (to be tied together externally). 3. v ainx may exceed v ss_adc0 and v dd_adc0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped res pectively to 0x000 or 0x3ff. 4. during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capaci tance to reach its final voltage level within t adc0_s . after the end of the sample time t adc0_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc0_s depend on programming. 5. this parameter does not include the sample time t adc0_s, but only the time for determining the digital result and the time to load the result's register with the conversion result. 6. refer to adc conversion tabl e for detailed calculations. 7. pb10 should not have any current injected. it can disturb accuracy on other adc_0 pins. 8. total unadjusted error: the maximum error that occurs wi thout adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 43. adc conversion characteristics (10-bit adc_0) (continued) symbol c parameter conditions (1) value unit min typ max docid17478 rev 9 93/123 spc564bxx-SPC56ECXX electrical characteristics 122 figure 20. adc_1 characteristic and error definitions (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 1 lsb ideal = avdd / 4096 electrical characteristics spc564bxx-SPC56ECXX 94/123 docid17478 rev 9 table 44. conversion characteristics (12-bit adc_1) symbol c parameter conditions (1) value unit min typ max v ss_adc1 sr ? voltage on vss_hv_adc1 (adc_1 reference) pin with respect to ground (v ss_hv ) (2) ? ? 0.1 0.1 v v dd_adc1 3 sr ? voltage on vdd_hv_adc1 pin (adc_1 reference) with respect to ground (v ss_hv ) ? v dd_hv_a ? ? 0.1 v dd_hv_a + 0.1 v v ainx (3), (4) sr ? analog input voltage (5) ? v ss_adc1 ? ? 0.1 v dd_adc1 + 0.1 v f adc1 sr ? adc_1 analog frequency ? 8 + 2% 32 + 2% mhz t adc1_pu sr ? adc_1 power up delay ? 1.5 s t adc1_s cc t sample time (6) vdd=5.0 v ? 440 ns sample time (6) vdd=3.3 v ? 530 t adc1_c cc p conversion time (7), (8) vdd=5.0 v f adc1 = 32 mhz 2 s conversion time (7), (6) vdd =5.0 v f adc 1 = 30 mhz 2.1 conversion time (7), (6) vdd=3.3 v f adc 1 = 20 mhz 3 conversion time (7), (6) vdd =3.3 v f adc1 = 15 mhz 3.01 c s cc d adc_1 input sampling capacitance ?5 pf c p1 cc d adc_1 input pin capacitance 1 ?3 pf c p2 cc d adc_1 input pin capacitance 2 ?1 pf docid17478 rev 9 95/123 spc564bxx-SPC56ECXX electrical characteristics 122 c p3 cc d adc_1 input pin capacitance 3 ?1.5 pf r sw1 cc d internal resistance of analog source ?1 k ? r sw2 cc d internal resistance of analog source ?2 k ? r ad cc d internal resistance of analog source ?0.3 k ? i inj sr ? input current injection current injection on one adc_1 input, different from the converte d one v dd = 3.3 v 10% ? 5 ? 5 ma v dd = 5.0 v 10% ? 5 ? 5 inlp cc t absolute integral non-linearity- precise channels no overload 1 3 lsb inls cc t absolute integral non-linearity- standard channels no overload 1.5 5 lsb dnl cc t absolute differential non- linearity no overload 0.5 1 lsb ofs cc t absolute offset error ?2 lsb gne cc t absolute gain error ?2 lsb tuep (9) cc p total unadjusted error for precise channels, input only pins without current injection ? 6 6 lsb t with current injection ? 8 8 lsb tues (9) cc t total unadjusted error for standard channel without current injection ? 10 10 lsb t with current injection ? 12 12 lsb 1. v dd = 3.3 v 10 % / 5.0 v 10 %, t a = ? 40 to 125 c, unless otherwise specified. 2. analog and digital v ss_hv must be common (to be tied together externally). table 44. conversion characterist ics (12-bit adc_1) (continued) symbol c parameter conditions (1) value unit min typ max electrical characteristics spc564bxx-SPC56ECXX 96/123 docid17478 rev 9 3.18 fast ethernet controller mii signals use cmos signal levels comp atible with devices operating at 3.3 v. signals are not ttl compatible. they follow the cmos electrical characteristics. 3.18.1 mii receive signal timing (rxd[3 :0], rx_dv, rx_er, and rx_clk) the receiver functions correctly up to a rx_clk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the system clock frequency must exceed four times the rx_clk frequency in 2:1 mode and two times the rx_clk frequency in 1:1 mode. figure 21. mii receive signal timing diagram 3. pa3, pa7, pa10, pa11 and pe12 adc_1 channels are coming from v dd_hv_b domain hence vdd_hv_adc1 should be within 100 mv of vdd_hv_b when these channels are used for adc_1. 4. vdd_hv_adc1 can operate at 5v condition while v dd_hv_b can operate at 3.3v provided that adc_1 channels coming from v dd_hv_b domain are limited in max swing as v dd_hv_b . 5. v ainx may exceed v ss_adc1 and v dd_adc1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped res pectively to 0x000 or 0xfff. 6. during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capaci tance to reach its final voltage level within t adc1_s . after the end of the sample time t adc1_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc1_s depend on programming. 7. conversion time = bit evaluation time + sampling time + 1 clock cycle delay. 8. refer to adc conversion tabl e for detailed calculations. 9. total unadjusted error: the maximum error that occurs wi thout adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 45. mii receive signal timing spec characteristic min max unit m1 rxd[3:0], rx_dv, rx_er to rx_clk setup 5? ns m2 rx_clk to rxd[3:0], rx_dv, rx_er hold 5? ns m3 rx_clk pulse width high 35% 65% rx_clk period m4 rx_clk pulse width low 35% 65% rx_clk period m1 m2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er m3 m4 docid17478 rev 9 97/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.18.2 mii transmit signal timing (t xd[3:0], tx_en, tx_er, tx_clk) the transmitter functions correctly up to a tx_clk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the system clock frequency must exceed four times the tx_clk frequency in 2:1 mode and two times the tx_clk frequency in 1:1 mode. the transmit outputs (txd[3:0], tx_en, tx_e r) can be programmed to transition from either the rising or falling edge of tx_clk, and the timing is t he same in either case. this options allows the use of non-compliant mii phys. refer to the fast ethernet controller (fec) chapter of the spc564b74 and spc56ec74 reference manual for details of this option and how to enable it. figure 22. mii transmit signal timing diagram 3.18.3 mii async inputs si gnal timing (crs and col) table 46. mii tran smit signal timing (1) spec characteristic min max unit m5 tx_clk to txd[3:0], tx_en, tx_er invalid 5? ns m6 tx_clk to txd[3:0], tx_en, tx_er valid ?25 ns m7 tx_clk pulse width high 35% 65% tx_clk period m8 tx_clk pulse width low 35% 65% tx_clk period 1. output pads configured with sre = 0b11. m6 tx_clk (input) txd[3:0] (outputs) tx_en tx_er m5 m7 m8 table 47. mii async inputs signal timing (1) spec characteristic min max unit m9 crs, col minimum pulse width 1.5 ? tx_clk period 1. output pads configured with sre = 0b11. electrical characteristics spc564bxx-SPC56ECXX 98/123 docid17478 rev 9 figure 23. mii async inputs timing diagram 3.18.4 mii serial management channel timing (mdio and mdc) the fec functions correctly with a maximum mdc frequency of 2.5 mhz. figure 24. mii serial manage ment channel timing diagram crs, col m9 table 48. mii serial ma nagement channel timing (1) spec characteristic min max unit m10 mdc falling edge to mdio output invalid (minimum propagation delay) 0? ns m11 mdc falling edge to mdio output valid (max prop delay) ?25 ns m12 mdio (input) to mdc rising edge setup 28 ? ns m13 mdio (input) to mdc rising edge hold 0 ? ns m14 mdc pulse width high 40% 60% mdc period m15 mdc pulse width low 40% 60% mdc period 1. output pads configured with sre = 0b11. m11 mdc (output) mdio (output) m12 m13 mdio (input) m10 m14 m15 docid17478 rev 9 99/123 spc564bxx-SPC56ECXX electrical characteristics 122 3.19 on-chip peripherals 3.19.1 current consumption table 49. on-chip peripherals current consumption (1) symbol c parameter conditions value (2) unit typ i dd_hv_a(can) cc d can (flexcan) supply current on v dd_hv_a 500 kbps total (static + dynamic) consumption: flexcan in loop-back mode xtal@8 mhz used as can engine clock source message sending period is 580 s 7.652 ? f periph + 84.73 a 125 kbps 8.0743 ? f periph + 26.757 i dd_hv_a(emios) cc d emios supply current on v dd_hv_a static consumption: emios channel off global prescaler enabled 28.7 ? f periph dynamic consumption: it does not change varying the frequency (0.003 ma) 3 i dd_hv_a(sci) cc d sci (linflex) supply current on v dd_hv_a total (static + dynamic) consumption: lin mode baudrate: 20 kbps 4.7804 ? f periph + 30.946 i dd_hv_a(spi) cc d spi (dspi) supply current on v dd_hv_a ballast static consumption (only clocked) 1 ballast dynamic consumption (continuous communication): baudrate: 2 mbit transmission every 8 s frame: 16 bits 16.3 ? f periph i dd_hv_a(adc) cc d adc supply current on v dd_hv_a v dd = 5.5 v ballast static consumption (no conversion) 0.0409 ? f periph ma v dd = 5.5 v ballast dynamic consumption (continuous conversion) 0.0049 ? f periph electrical characteristics spc564bxx-SPC56ECXX 100/123 docid17478 rev 9 3.19.2 dspi characteristics idd_hv_adc0 cc d adc_0 supply current on v dd_hv_adc0 v dd = 5.5 v analog static consumption (no conversion) 200 a analog dynamic consumption (continuous conversion) 4ma idd_hv_adc1 cc d adc_1 supply current on v dd_hv_adc1 v dd = 5.5 v analog static consumption (no conversion) 300 a v dd = 5.5 v analog dynamic consumption (continuous conversion) 6ma i dd_hv(flash) cc d cflash + dflash supply current on v dd_hv_adc v dd = 5.5 v ? 13.25 ma i dd_hv(pll) cc d pll supply current on v dd_hv v dd = 5.5 v ? 0.0031 ? f periph 1. operating conditions: t a = 25 c, f periph = 8 mhz to 120 mhz. 2. f periph is in absolute value. table 49. on-chip peripherals current consumption (1) symbol c parameter conditions value (2) unit typ table 50. dspi timing spec characteristic symbol value unit min max 1 dspi cycle time t sck refer note (1) ?ns ? internal delay between pad associated to sck and pad associated to csn in master mode for csn1->0 ? t csc ? 115 ns ? internal delay between pad associated to sck and pad associated to csn in master mode for csn1->1 ? t asc 15 ? ns 2 cs to sck delay (2) t csc 7?ns 3 after sck delay (3) t asc 15 ? ns 4 sck duty cycle t sdc 0.4 ? t sck 0.6 ? t sck ns docid17478 rev 9 101/123 spc564bxx-SPC56ECXX electrical characteristics 122 ? slave setup time (ss active to sck setup time) t suss 5?ns ? slave hold time (ss active to sck hold time) t hss 10 ? ns 5 slave access time (ss active to sout valid) (4) t a ? 42 ns 6 slave sout disable time (ss inactive to sout high-z or invalid) t dis ? 25 ns 7 csx to pcss time t pcsc 0?ns 8pcss to pcsx time t pasc 0?ns 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) (5) master (mtfe = 1, cpha = 1) t sui 36 5 36 36 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) (5) master (mtfe = 1, cpha = 1) t hi 0 4 0 0 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 12 37 12 12 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho 0 (6) 9.5 0 (7) 0 (8) ? ? ? ? ns ns ns ns 1. this value of this parameter is dependent upon the external device delays and the other parameters mentioned in this table. 2. the maximum value is programmable in dspi_ctar n [pssck] and dspi_ctar n [cssck]. for spc564b74 and spc56ec74, the spec value of t csc will be attained only if t dspi x pssck x cssck > ? t csc . 3. the maximum value is programmable in dspi_ctar n [pasc] and dspi_ctar n [asc]. for spc564b74 and spc56ec74, the spec value of t asc will be attained only if t dspi x pasc x asc > ? t asc. 4. the parameter value is obtained from t suss and t suo for slave. 5. this number is calculated assuming the smpl _pt bitfield in dspi_mcr is set to 0b00. 6. for dspi1, the data hold time for outputs in master (mtfe = 0) is ? 2 ns. 7. for dspi1, the data hold time for outputs in master (mtfe = 1, cpha = 0) is ? 2 n. 8. for dspi1, the data hold time for outputs in master (mtfe = 1, cpha = 1) is ? 2 ns. table 50. dspi timing (continued) spec characteristic symbol value unit min max electrical characteristics spc564bxx-SPC56ECXX 102/123 docid17478 rev 9 figure 25. dspi classic spi timing?master, cpha = 0 figure 26. dspi classic spi timing?master, cpha = 1 data last data first data first data data last data sin sout csx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference table 50 . data last data first data sin sout 12 11 10 last data data first data sck output sck output csx 9 (cpol = 0) (cpol = 1) note: numbers shown reference table 50 . docid17478 rev 9 103/123 spc564bxx-SPC56ECXX electrical characteristics 122 figure 27. dspi classic spi timing?slave, cpha = 0 figure 28. dspi classic spi timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference table 50 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference table 50 . electrical characteristics spc564bxx-SPC56ECXX 104/123 docid17478 rev 9 figure 29. dspi modified transfer format timing?master, cpha = 0 figure 30. dspi modified transfer format timing?master, cpha = 1 csx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference table 50 . csx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference table 50 . docid17478 rev 9 105/123 spc564bxx-SPC56ECXX electrical characteristics 122 figure 31. dspi modified transfer format timing?slave, cpha = 0 figure 32. dspi modified transfer format timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference table 50 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference table 50 . electrical characteristics spc564bxx-SPC56ECXX 106/123 docid17478 rev 9 figure 33. dspi pcs strobe (pcss ) timing 3.19.3 nexus characteristics csx 7 8 pcss note: numbers shown reference table 50 . table 51. nexus debug port timing (1) spec characteristic symbol min max unit 1 mcko cycle time (2) t mcyc 16.3 ? ns 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo, mseo , evto data valid (3) t mdov ?0.1 0.25 t mcyc 4evti pulse width t evtipw 4.0 ? t tcyc 5evto pulse width t evtopw 1t mcyc 6 tck cycle time (4) t tcyc 40 ? ns 7 tck duty cycle t tdc 40 60 % 8 tdi, tms data setup time t ntdis, t ntmss 8?ns 9 tdi, tms data hold time t ntdih, t ntmsh 5?ns 10 tck low to tdo data valid t jov 025ns 1. jtag specifications in this table apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respecti ve signal. nexus timing specified at v dde = 4.0 ? 5.5 v, t a = t l to t h , and c l = 30 pf with src = 0b11. 2. mcko can run up to 1/2 of full system frequency. it can also run at system frequency when it is <60 mhz. 3. mdo, mseo , and evto data is held valid until next mcko low cycle. 4. the system clock frequency needs to be three times faster than the tck frequency. docid17478 rev 9 107/123 spc564bxx-SPC56ECXX electrical characteristics 122 figure 34. nexus output timing 1 2 mcko mdo mseo evto output data valid 3 evti 4 5 electrical characteristics spc564bxx-SPC56ECXX 108/123 docid17478 rev 9 figure 35. nexus tdi, tms, tdo timing 3.19.4 jtag characteristics tdo 8 9 tms, tdi 10 tck 6 7 table 52. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 64 ? ? ns 2t tdis cc d tdi setup time 10 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 4t tmss cc d tms setup time 10 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns 6t tdov cc d tck low to tdo valid ? ? 33 ns docid17478 rev 9 109/123 spc564bxx-SPC56ECXX electrical characteristics 122 figure 36. timing diagram - jtag boundary scan 7t tdoi cc d tck low to tdo invalid 6 ? ? ns ?t tdc cc d tck duty cycle 40 ? 60 % ?t tckrise cc d tck rise and fall times ? ? 3 ns table 52. jtag characteristics (continued) no. symbol c parameter value unit min typ max input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference table 52 . 3/5 2/4 7 6 package characteristics spc564bxx-SPC56ECXX 110/123 docid17478 rev 9 4 package characteristics 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 4.2 package mechanical data 4.2.1 lqfp176 package mechanical drawing figure 37. lqfp176 package mechanical drawing ccc c seating plane c aa2 a1 c 0.25 mm gauge plane hd d a1 l l1 k 89 88 ehe 45 44 e 1 176 pin 1 identification b 133 132 1t_me zd ze docid17478 rev 9 111/123 spc564bxx-SPC56ECXX package characteristics 122 table 53. lqfp176 mechanical data (1) symbol mm inches (2) min typ max min typ max a 1.400 1.600 0.063 a1 0.050 0.150 0.002 a2 1.350 1.450 0.053 0.057 b 0.170 0.270 0.007 0.011 c 0.090 0.200 0.004 0.008 d 23.900 24.100 0.941 0.949 e 23.900 24.100 0.941 0.949 e 0.500 0.020 hd 25.900 26.100 1.020 1.028 he 25.900 26.100 1.020 1.028 l (3) 0.450 0.750 0.018 0.030 l1 1.000 0.039 zd 1.250 0.049 ze 1.250 0.049 q0 7 0 7 tolerance mm inches ccc 0.080 0.0031 1. controlling dimension: millimeter. 2. values in inches are converted from mm and rounded to 4 decimal digits. 3. l dimension is measured at gauge plane at 0.25 mm above the seating plane. package characteristics spc564bxx-SPC56ECXX 112/123 docid17478 rev 9 4.2.2 lqfp208 package mechanical drawing figure 38. lqfp208 mechanical drawing note: exact shape of each corner is optional. docid17478 rev 9 113/123 spc564bxx-SPC56ECXX package characteristics 122 table 54. lqfp208 mechanical data ref mm mm min typ max min typ max a1.61.6 a1 0.05 0.15 0.05 0.1 0.15 a2 1.3 1.35 1.45 1.3 1.35 1.45 b 0.17 0.27 0.17 0.22 0.27 c 0.09 0.2 0.11 0.15 0.19 d 30 29.8 30 30.2 d1 28 27.8 28 28.2 d3 25.5 25.5 e0.5 0.5 e 30 29.8 30 30.2 e1 28 27.8 28 28.2 e3 25.5 25.5 l 0.45 0.6 0.75 0.4 0.5 0.6 l1 1 1 k 0 3.5 7.0 1 3 5 package characteristics spc564bxx-SPC56ECXX 114/123 docid17478 rev 9 4.2.3 lbga256 package mechanical drawing figure 39. lbga256 mechanical drawing docid17478 rev 9 115/123 spc564bxx-SPC56ECXX package characteristics 122 note: the package is designed according to the jedec standard no 95-1 section 14 dedicated to ball grid array pack age design guide. table 55. lbga256 mechanical data ref mm min typ max a 1.210 1.700 a1 0.300 a2 0.300 a4 0.800 b 0.400 0.500 0.600 d 16.800 17.000 17.200 d1 15.000 e 16.800 17.000 17.200 e1 15.000 e 0.900 1.000 1.100 z 0.750 1.000 1.250 ddd 0.200 ordering information spc564bxx-SPC56ECXX 116/123 docid17478 rev 9 5 ordering information figure 40. ordering information scheme memory conditioning core family temperature package cpu frequency spc56 74 y 4c c l7 e example code: product identifier y = tray ? x = tape and reel ? ? ? 0 = no option ? e = ethernet ? c = cse + ethernet ? ? ? ? 0 = no eeprom ? e = eeprom ? ? ? ? 8 = 80 mhz ? 9 = 120 mhz ? ? ? ? b = ?40 to 105 c ? c = ?40 to 125 c ? ? l7 = lqfp176 l8 = lqfp208 ? b3 = lbga256 ? ? 74 = 3 mb ? 70 = 2 mb ? 64 = 1.5 mb ? ? b = body ? c = gateway ? ? 4 = e200z4d ? e = e200z4d + e200 z0h ? spc56 = power architecture in 90 nm 8 0 eeprom options docid17478 rev 9 117/123 spc564bxx-SPC56ECXX abbreviations 122 appendix a abbreviations table 56 lists abbreviations used but not defined elsewhere in this document. table 56. abbreviations abbreviation meaning cs chip select evto event out mcko message clock out mdo message data out mseo message start/end out mtfe modified timing format enable sck serial communications clock sout serial data out tbd to be defined tck test clock input tdi test data input tdo test data output tms test mode select revision history spc564bxx-SPC56ECXX 118/123 docid17478 rev 9 revision history table 57 summarizes revisions to this document. table 57. revision history date revision changes 01-jun-2010 1 initial release 17-dec-2010 2 ? editing and formatting updates throughout the document. ? updated voltage regulator capacitance connection figure . ? added a new sub-section ?v dd_bv options? ? program and erase specifications: ? updated tdwprogram typ to 22 us ? updated t128kpperase max to 5000 ms ? added t esus parameter ? added recommendation in the voltage regulator electrical characteristics section. ? added crystal description table in fast external crystal oscillator (4 to 140 mhz) electrical characteristics section and co rrected the cross-reference to the same. ? added new sections - pad types, system pins and functional ports ? updated typ numbers in the flash progr am and erase specifications table ? added a new table: program and erase specifications (data flash) ? flash read access timing table: added data flash memory numbers ? flash power supply dc electrical char acteristics table: updated idfread and idfmod values for data flas h, removed idflpw parameter ? updated feature list. ? spc564bxx and SPC56ECXX family comparison table: updated adc channels and added adc footnotes. ? spc564bxx and SPC56ECXX block diagram: updated adc channels and added legends. ? spc564bxx and SPC56ECXX series block summary: added new blocks. ? functional port pin descriptions table: added osc32k_xtal and osc32k_extal function at pb8 and pb9 port pins. ? electrical characteristics: replaced vss with vss_hv throughout the section. ? absolute maximum ratings, recommended operating conditions (3.3 v) and recommended operating conditions (5.0 v) tables: vrc_ctrl min is updated to "0". ? recommended operating conditions (3.3 v) and recommended operating conditions (5.0 v) tables: clarified vin parameter, clarified footnote 2 in both tables. ? lqfp thermal characteristics section: added numbers for lqfp packages. ? low voltage power domain electrical ch aracteristics table: clarified footnotes based upon review comments. ? code flash memory?program and erase specifications: updated tesrt to 20 ms. ? adc electrical characteristics secti on: replace adc0 with adc_0 and adc1 with adc_1 throughout the document. dspi characteristics section: replaced pc sx with csx in all figures and tables. docid17478 rev 9 119/123 spc564bxx-SPC56ECXX revision history 122 28-apr-2011 3 ? replaced vil min from ?0.4 v to ?0.3 v in the following tables: ? - i/o input dc electrical characteristics ? - reset electrical characteristics ? - fast external crystal oscillator (4 to 40 mhz) electrical characteristics ? updated crystal oscillator and resonator connection scheme figure ? specified npn transistor as the recommended bcp68 transistor throughout the document ? code and data flash memory?program and erase specifications tables: renamed the parameter t esus to t eslat ? revised the footnotes in the ?functional port pin descriptions? table. ? in the ?system pin descriptions? table, added a footnote to the a pads regarding not using ibe. ? for ports pb[12?15], changed anx to adc0_x. ? revised the presentation of the ad c functions on the following ports: pb[4?7] pd[0?11] ? adc conversion characteristics (10-bit adc_0) table and conversion characteristics (12-bit adc_1) table- up dated footnote 5 and 7 respectively for the definition of the conversion time. ? data flash memory?program and erase specifications: updated t wprogram to 500 s and t 16kpperase to 500 s. corrected teslat classsification from ?c? to ?d?. ? code flash memory?program and erase specifications: corrected teslat classification from ?c? to ?d?. ? flash start-up time/switch-off time: changed t flarstexit classification from ?c? to ?d?. ? functional port pin description: added a footnote at the pb [9] port pin. ? absolute maximum ratings table: added footnote 1. ? low voltage power domain electrical characteristics table: updated iddhalt, iddstop, iddstby3, iddstdby2, iddstdby1. ? updated commercial product code structure. ? slow external crystal oscillator (32 khz) electrical characteristics table: updated g msxosc , v sxosc , i sxoscbias and i sxosc. ? fmpll electrical characteristics table: updated ? t ltjit. ? fast internal rc oscillator (16 mhz) electrical characteristics table: updated tfircsu and ifircpwd. ? mii serial management channel timing table: updated m12 ? jtag characteristics table: updated t tdov. ? low voltage monitor electrical characteristics table: updated vlvdhv3h, vlvdhv3l, vlvdhv5h, vlvdhv5l. ? dspi electricals table: updated spec 1, 5, 6. updated fo otnote 2 and 3. added ? t csc , ? t asc , t suss , t hss. ? io consumption table: updated all parameter values. ? dspi electricals: updated ? t csc max to 115 ns. ? low voltage power domain electrical characteristics table: added footnote 9. ? adc electrical characteristics: added 2 notes above 10-bit and 12-bit conversion tables. table 57. revision history (continued) date revision changes revision history spc564bxx-SPC56ECXX 120/123 docid17478 rev 9 01-dec-2011 4 ? interchanged the denominator with numerator in equation 11 of input impedance and adc accuracy section ? removed the note (all adc conversion c haracteristics described in the table below are applicable only for the precision channels. the data for semi-precision and extended channels is awaited and same will be subsequently updated in later revs.) in the adc electr ical characteristics section. ? table 49 (on-chip peripherals current co nsumption). replaced idd_hv_adc with idd_hv_adc0 and idd_hv_adc1 values as per adc specs ?in table 43 , the minimum sample time of adc0 changed to 500 at 32 mhz ?in table 43 , removed the entry for sample time at 30 mhz ?in table 44 , changed tuex to tues and inlx to inls (extended channels are not supported by the device. so, changed to standard channel.) 04-mar-2013 5 ? updated the pins 23 and 24 of figure 2: 176-pin lqfp configuration . ? updated unit of measure in table 44: conversion characteristics (12-bit adc_1) ? modified the value to typical value in table 49: on-chip peripherals current consumption ? added footnote to t esrt parameter in table 26: code flash memory?program and erase specifications ? added footnote to t esrt parameter in table 27: data flash memory?program and erase specifications ? updated table 29: flash memory read access timing . ? updated notes 2 and notes 3 of table 10: recommended operating conditions (3.3 v) and table 11: recommended operating conditions (5.0 v) respectively. ? updated the footnote1 of table 10: recommended operating conditions (3.3 v) and table 11: recommended operating conditions (5.0 v) ? updated v dd_hv_a to v dd_bv for c dec2 and i dd_hv_a in table 23: voltage regulator electrical characteristics and deleted footnote3 ? updated the dedicated number of channels for 12-bit adc in family comparison tables ? updated the values of f sirc, parameters and conditions of ? sircvar in table 41: slow internal rc oscillator (128 khz) electrical characteristics ? updated second footnote in table 11: recommended operating conditions (5.0 v) , ? updated the value of t adc0_pu in table 43: adc conversion characteristics (10- bit adc_0) ? updated the idd values in table 25: low voltage power domain electrical characteristics ? added footnote to table 25: low voltage power domain electrical characteristics related to current drawn from v dd_hv_a and v dd_hv_b ? updated entire section 3.17.1.1: input impedance and adc accuracy ? updated the values of vlpreg in table 23: voltage regulator electrical characteristics . ? updated the values of v lpreg in table 23: voltage regulator electrical characteristics . ? added t a = 25 c, min and max values of v mreg in table 23: voltage regulator electrical characteristics ? added t a = 25 c, min and max values of v lpreg in table 23: voltage regulator electrical characteristics table 57. revision history (continued) date revision changes docid17478 rev 9 121/123 spc564bxx-SPC56ECXX revision history 122 04-mar-2013 5 (cont.) ? updated the min, max and typical values of v lvdlvcorl and v lvdlvbkpl in table 24: low voltage monitor electrical characteristics ? updated values of gmfxosc in table 36: fast external cr ystal oscillator (4 to 40 mhz) electrical characteristics ? updated values of gmsxosc in table 38: slow external crystal oscillator (32 khz) electrical characteristics ? updated the footnote 5 for t adc0_c in table 43: adc conversion characteristics (10-bit adc_0) ? updated the footnotes of table 25: low voltage power domain electrical characteristics 17-sep-2013 6 ? updated disclaimer 28-nov-2014 7 ? removed occurrences of 208bga from table 2: spc564bxx and SPC56ECXX family comparison . ? added pm[3] and pm[4] in the figure note 1 of figure 4: 256-pin bga configuration . ? added a table note in table 20: i/o supplies . ? updated figure 8: voltage regulator capacitance connection and added a note in this figure. ? removed before trimming value for v mreg , updated after trimming min value of v mreg from 1.24 v to 1.20 v, updated after trimming min value of v lpreg from 1.225 v to 1.17 v, updated after trimming typical value of v lpreg from 1.25 v to 1.27 v and updated after trimming max value of v lpreg from 1.275 v to 1.32 v in table 23: voltage regulator electrical characteristics . ? changed min value of v lvdlvcorl and v lvdlvbkpl from 1.12 v to 1.08 v, and removed typical value of v lvdlvcorl and v lvdlvbkpl in table 24: low voltage monitor electrical characteristics ? updated max values at 120 mhz for i ddrun from 200 ma to 208 ma and from 270 ma to 280 ma; updated max value at t a = 125 c for i ddhalt from 80 ma to 100 ma ; updated max value at t a = 25 c for i ddstop from 1.2 ma to 5 ma and at t a = 125 c from 60 ma to 72 ma; updated max value at t a = 25 c for i ddstdby3 from 75 a to 96 a and at t a = 125 c from 1200 a to 2400 a; updated max value at t a = 25 c for i ddstdby2 from 70 a to 92 a and at t a = 125 c from 1100 a to 2000 a; updated max value at t a = 25 c for i ddstdby1 from 65 a to 85 a and at t a = 125 c from 650 a to 1100 a; updated 1st footnote in table 25: low voltage power domain electrical characteristics . ? added a footnote below table 29: flash memory read access timing . ? updated the formula in eq. 11 in section 3.17.1.1: input impedance and adc accuracy . ? updated legend in figure 16: input equivalent circuit (precise channels) ? updated min and max values for g mfxosc at v dd = 5.0 v 10% from 4 ma/v to 6.5 ma/v and from 20 ma/v to 25 ma/v in table 36: fast external crystal oscillator (4 to 40 mhz) electrical characteristics ? added figure 17: input equivalent circuit (extended channels) . ? updated t adc0_pu value to 1.5 as max and added footnote for i inj in table 43: adc conversion characteristics (10-bit adc_0) . table 57. revision history (continued) date revision changes revision history spc564bxx-SPC56ECXX 122/123 docid17478 rev 9 28-nov-2014 7 (cont.) ? added category column in table 44: conversion characteristics (12-bit adc_1) . ? added the idd_hv_adc0 values in table 49: on-chip peripherals current consumption . 16-jun-2015 8 updated figure 37: lqfp176 package mechanical drawing and figure 40: ordering information scheme . 11-mar-2016 9 ? added package silhouette on the cover page ? removed figure 4: lbga208 configuration ? removed lbga208 column in table 4: system pin descriptions and in table 5: functional port pin descriptions ? table 12: lqfp thermal characteristics : for ?r ? ja ? row, changed max value relating to conditions ?single-layer board?1s? and ?four-layer board?2s2p? from ?tbd? to ?43? and ?33.9?, respectively ? removed table 13: lbga208 ther mal characteristics ? table 13: lbga256 thermal characteristics : for ?r ? ja ? row, changed max value relating to conditions ?single-layer board?1s? and ?four-layer board?2s2p? from ?tbd? to ?44.3? and ?31?, respectively ? removed lbga208 row in table 20: i/o supplies ? removed section 4.2.3: lbga208 package mechanical drawing ?in table 25: low voltage power domain electrical characteristics , updated notes ?only for the ?p? classification: lpreg on, hpvreg off, 96 kb ram on, device configured for...?, ?lpreg on, hpvreg off, 64 kb ram on, device configured for...?, and ?lpreg on, hpvreg off, 8 kb ram on, device configured for...? ?in table 49: on-chip peripherals current consumption , changed idd_hv_adc1 value from ?300 f periph ? to ?300? table 57. revision history (continued) date revision changes docid17478 rev 9 123/123 spc564bxx-SPC56ECXX 123 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
Price & Availability of SPC56ECXX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |